【作者】 赵家阳；

【导师】 李野；

【作者基本信息】 长春理工大学 ， 微电子学与固体电子学， 2008， 硕士

【摘要】 随着数字通信系统的发展,高速数字处理系统对模拟信号和数字信号之间的转换要求越来越高。高速模数转换器已经成为当今模拟集成电路的研究热点本文设计了一个12位40 M流水线结构模数转换器(ADC)。综合考虑到面积、速度和功耗,该ADC由4级分别为5位、3位、3位、4位流水线级构成。从影响ADC性能的各种非理想因素入手,在逐一改善这些非理想因素影响的过程中得到电路的具体结构。本文主要针对采样保持电路和静态功耗较小的动态比较器进行研究,ADC中每个模块都通过了功能仿真,达到了所需要的性能指标。本设计可用于信号处理,或作为SOC芯片的一个IP核。更多还原

【Abstract】 With the development of modem digital communication systems,high-speed digital processing system creates a great demand for high conversion rate between analog signal and digital signal,and high-speed ADC has gained a lot of importance and interst.A 12-bit 40 MS/s pipeline A/D converter is designed in this paper.Extensively consideration for the speed,area and its power dissipation,the structure design is consist of 4 stages pipelined containing 5 bit,3 bit,3 bit,4 bit individually.Analyzing the nonideal factors at the beginning and with improving all of this one by one the architecture of ADC is got.This thesis focuses on the research of S/H circuit and low-power dynamic comparator. All modules in the ADC are successfully simulated,and reach the demands of ADC.This chip can be used in signal process or embedded in SOC chip as an IP core.更多还原