【作者】 李争；

【导师】 李哲英；

【作者基本信息】 北京交通大学 ， 微电子学与固体电子学， 2008， 硕士

【摘要】 锁相环发展迅速,应用广泛,使其成为当前模拟集成电路的核心技术之一。作为通讯系统应用最为广泛的一个模块,锁相环在高速处理器的时钟产生中有着广泛的应用。处理器这类大型的数字电路在其翻转过程中将产生严重的电源、衬底噪声,这些噪声及处理器本身固有的器件噪声会对锁相环的工作性能产生极大的影响。本文针对电荷泵锁相环结构,进行了深入的理论分析,从系统的角度分析了如何减少锁相环的噪声,建立了环路对锁相环各噪声源的传递函数,并据此确定了环路参数和系统结构,根据系统的响应速度、稳定性、对噪声的抑制能力等对系统参数如何确定展开了讨论。接下来优化各模块设计来减少锁相环的噪声,对鉴频鉴相器的死区、电荷泵电流匹配、电荷共享问题、片上集成螺旋电感都作了深入研究,并采用自顶向下的方法设计了一个低噪声CMOS电荷泵锁相环。根据给定的性能指标要求,完成了系统设计,电路设计直到版图设计,并最终由IC生产厂完成芯片制造。生成高速,稳定的时钟信号是本课题的目标。更多还原

【Abstract】 PLL is developing rapidly, that make it to be the most important core technology of current analog IC. As the most widely used module in communications system, the PLL clock is much useful in a high speed processor. Processors, such large scale digital circuits, in its turnover process will have a serious power noise and substrate noise, further more, the inherent noise of the devices in processors also has great impact on phase locked loop. Aimed at charge pump PLL, the paper analysis the theory deeply, and how to reduce the noise of PLL from the view of system, and established the noise transfer function of the PLL loop, then identified loop parameters and system architecture. It also discussed about how to determine the parameters of the system according to the response speed, stability, and the capability for noise suppression. In another hand the module had been optimized to reduce the noise in PLL. The dead zone of PFD, the current match of charge pump, charge sharing issues, on chip spiral inductors are studied deeply. By adopting the top-down method, a CMOS low noise charge pump phase locked loop is designed. According to the requirements performance indicators are set. From the system design, circuit design to layout design, PLL is completed, and eventually realized by the IC chip fabrication. Generating high speed and stable clock signal is the objective of this subject.更多还原