【作者】 高超；

【导师】 殷福亮； 陈喆；

【作者基本信息】 大连理工大学 ， 信号与信息处理， 2007， 硕士

【摘要】 随着现代空间技术的发展，星载图像处理技术在军事侦察、森林防火、地质勘查等方面得到了广泛应用。卫星、飞船和空间站等对地观测空间飞行器能否将数据实时地从空间传送到地面，是衡量这些航天计划成败的标准之一。然而星载图像的数据量一般都较大，而且信道传输带宽有限，所以必须采用数据压缩的方法来减少传输数据量。空间数据系统咨询委员会(Consultative Committee for Space Data System)于2005年11月正式提出CCSDS空间图像数据压缩算法标准。该算法复杂度低，结构简单，易于硬件实现，支持空间图像的高速实时处理。本文的目的是在FPGA芯片上实现CCSDS图像数据压缩算法。在整个系统的实现过程中，主要完成的工作有：(1)深入研究CCSDS图像压缩算法，并从算法性能和硬件实现复杂度两个方面，将该算法与JPEG2000和SPIHT图像压缩算法进行比较分析；(2)用硬件描述语言Verilog HDL在FPGA上实现CCSDS图像压缩算法，并优化算法复杂度较大的功能模块，如小波变换模块，其优化方法包括：使用移位加代替乘法和除法运算，采用流水线设计提高时钟频率，引入行列变换并行结构提高并行度，使用双端口内存模块增加数据读写速度；(3)在ISE和ModelSim仿真环境下对该系统进行模块级和系统级的前仿真、后仿真和验证。在硬件系统测试阶段，设计并实现FPGA与PC机的串口通信模块，提高了系统验证的工作效率。本文在Xilinx公司Virtex-Ⅱ系列的XC2V2000芯片上实现了CCSDS图像压缩算法，并通过大量图像测试，验证了该系统的有效性。更多还原

【Abstract】 Along with the development of modern space technology, space image processing is widely used in military scout, geological reconnoitre, forest fireproofing and so on. It is a crucial task for satellites, airships, and space stations to send the real-time information to the earth. But the data volume of space image is always very big, and channel capability is limited. For reduce the data volume, it is necessary to compress the image data.CCSDS (Consultative Committee for Space Data System) formally proposed the space image data compression algorithm standard in November, 2005. This recommendation has a low complexity and simple structure to fit for hardware implementation, and support high speed real-time space image processing. In this thesis, CCSDS image compression algorithm is implemented on FPGA. The main accomplished tasks of this thesis include the following parts:(1) The CCSDS coding algorithm is studied deeply, and compared with JPEG2000 and SPIHT algorithms on complexity and performance.(2) The CCSDS image coding algorithm is implemented on FPGA using Verilog HDL and the complex modules are optimized, like the discrete wavelet transform, its optimizing methods include: shift and addition is used to replace the multiplication and division; pipeline technique is used to raise the clock frequency; row and column DWT parallel technique is introduced to reduce the number of clock cycles.(3) The whole system is simulated and verified functionally and timingly in ISE and ModelSim environments, the RS232 serial port is designed at the stage of FPGA hardware verification to reduce the verification time.The CCSDS image compression system is implemented successfully on XC2V2000 of Xilinx Virtex-II series. The system is verified on the effectivity and performance by a number of test images.更多还原