【作者】 陈庆伟；

【导师】 高金山；

【作者基本信息】 北京交通大学 ， 计算机系统结构， 2008， 硕士

【摘要】 本文研究了基于NiosⅡ的FPGA-CPU调试技术。论文研究了NiosⅡ嵌入式软核处理器的特性；实现了以NiosⅡ嵌入式处理器为核心的FPGA-CPU调试系统的软、硬件设计；对两种不同类型的FPGA-CPU进行了实际调试，对实验数据进行了分析。在硬件方面，为了控制和检测FPGA-CPU，设计并实现了FPGA-CPU的控制电路、FPGA-CPU的内部通用寄存器组扫描电路、存储器电路等；完成了各种外围设备接口的设计；实现了调试系统的整体设计。在软件方面，设计了调试监控软件，完成了对FPGA-CPU运行的控制和信号状态的监测。这些信号包括地址和数据总线以及各种寄存器的数据等；实现了多种模式下的FPGA-CPU调试支持单时钟调试、单步调试和软件断点多种调试模式。此外，设计了专用的编译软件，实现了基于不同指令系统的伪汇编程序编译，提高了调试效率。本文在实现了FPGA-CPU调试系统基础上，对两种指令系统不同、结构迥异的FPGA-CPU进行实际调试。调试结果表明，这种基于IP核的可复用设计技术，能够在一个FPGA芯片内实现调试系统和FPGA-CPU的无缝连接，能够有效地调试FPGA-CPU。更多还原

【Abstract】 In this paper, the technology of FPGA-CPU debugging is discussed based on Nios II embedded processor. The characteristics of Nios II embedded processor is studied. The hardware and software design of the FPGA-CPU debugging system are accomplished. Two different types of FPGA-CPU are debugged with the debug system developed . The testing datum are analyzed.As for hardware design, in order to control and monitor FPGA-CPU, several circuits are designed, which are the dual-port memory circuit, control circuit and scanning circuit etc. Besides, all inferface circuits between debuging system and FPGA-CPU are achievedAs for software design, the debuging software based on Nios II processor is completed, which can operate the dual-port memory, loading and controling testing programms. The software can monitor the FPGA-CPU running state. All information inside the FPGA-CPU can be obtainded , including registers , data bus and address bus etc. Several debuging mode are accomplished. They are single clock debugging model, one-step instruction debugging model, and breakpoint debugging model. These modes can be used alone or alternately.In order to increase the efficiency of the debuging system, a compiler software has been completed, with which the assembler programmers can be compiled into their machine language.On the implementation of debugging system, two types of FPGA-CPU are tested, whose instruction system and architecture are widely different. The debuging result demonstrates that the technology of debugging based on IP reuse can debug FPGA-CPU efficiently. The debuging system and the FPGA-CPU can be in one chip, achieving the seamless linking between the these parts.更多还原