【作者】 范俊；

【导师】 周功业；

【作者基本信息】 华中科技大学 ， 计算机系统结构， 2006， 硕士

【摘要】 SATA(Serial ATA)是一种高速的串行总线,采用点对点方式进行数据传输,内置数据/命令校验单元,支持热插拔,具有150MB/s(SATA 1.0)或300MB/s(SATA 2.0)传输速度。目前SATA应用广泛,但国内尚无独立研发的SATA芯片。分析了SATA协议标准,建立了SATA主机控制器的层次结构,将SATA控制器划分成主机接口层、ATA适配层、传输层、链路层和物理层,各层之间采用异步FIFO(First In First Out)通讯。实现了多状态机的协同设计,完成了高速并行CRC编解码器、并行8B/10B编解码器和基于线性回馈移位寄存器的加密解密器件的设计,实现了1.5Gbps的自动阻抗匹配的串行传输通道。实现了133MHz高速PCI主机接口,支持32/64位可配置总线宽度,支持地址配置空间,具有主控DMA功能。分析并测试了FIFO深度及性能,计算了FIFO深度对层间并行运行度的影响。进行了SATA控制器的运行测试,与同类商用产品性能相当。编写了智能化仿真验证向量脚本,对整个设计进行对称封装测试,保证设计的正确性和健壮性。运用低功耗的设计理念和流水线设计技巧,对仿真验证后的设计进行了优化和重构,节约了现场可编程门阵列(Field Programmable Gate Array,FPGA)可综合资源,增加了芯片的运行速度。深入探讨了芯片设计的自动化方法,使用一种新的描述模型取代传统的编码过程。给出了一个可视化操作环境,使用这个模型描述的设计任务,能直接转换成芯片可综合的逻辑描述,实现部分集成电路的设计自动化。更多还原

【Abstract】 Serial ATA (SATA) is a high speed serial bus. It has point to point transfer mode, embedded data and commands checking unit, support hot plug and play, the band wide is 150MB per second (SATA version 1.0) or 300MB/s (SATA version 2.0). The product of SATA is widely used, but the entire products are provided from abroad, no chips developed on an independent basis. In the Embedded area, no SATA chip being provided right now.Analyzed SATA protocol, developed a stack layer model of SATA adapter, the stack model contains a host interface layer, an ATA simulation layer, a transport layer, a link layer and a physical layer. Asynchronous FIFO is arranged to communicate between the layers. Implement multiple state machine cooperation design. Designed high speeds parallel CRC encode decode unit, and parallel 8b to 10b encoder/decoder, and scrambling unit using line feedback shift register. Implement 1.5Gbps differential serial signal communications channel. Implement 133MHz max speed PCI host interface, 32/64 parametric bus width, with address configuration space and DMA. Analyzed and tested the depth and performance of FIFO, calculated the FIFO depth’s affection to parallel degree of the stack layer. Tested the performance of SATA Adapter, the working performance is as good as commercial product. Write simulation verification script, it make the RTL code work correctly. Gives an IC design automation model, use a new description strategy, it can translate the design task to synthetic HDL code, and can be used to a wide classic of chips.更多还原