【作者】 张小军；

【导师】 陈新华；

【作者基本信息】 山东科技大学 ， 计算机应用技术， 2007， 硕士

【摘要】 片上系统(System on Chip，SoC)技术是21世纪集成电路发展的重要方向。本论文来源于导师的教育厅重点科研项目“基于嵌入式SoC智能信息家电集成电路的研究与设计”，主要开展了关于SoC软核的研究与设计，设计了一个基于8051 IP核的SoC系统平台。该系统平台应用8051 IP软核为微控制器，选择易于与MCU连接的Wishbone总线作为系统总线。通过外部RAM的访问时序以模拟Wishbone总线的时序，实现了Wishbone总线与8051的桥接。外扩了一个通用的I／O口(P4端口)，设计了家用电器常用的三个IP软核SPI、I~2C和PWM控制器，增强了8051 IP控制器的功能，成功搭建了家用电器的控制器SoC开发平台。在此基础上，实现了一个无线数据采集系统。本平台应用QuartusⅡEDA集成开发工具进行设计，用MENTOR公司的ModelsimSE 6.2b仿真软件，对各个软核进行了较完整的测试仿真。使用Synplify Pro 8.1进行综合，得到了符合要求的电路和门级网表。以Altera的CycloneⅡ组成的DE2实验板为验证平台，采用I~2C总线接口的存储器AT24C64芯片和SPI总线接口的无线模块PTR8000，搭建了无线数据采集测试系统。经测试，各个模块运行正常，各项指标满足系统的需要，达到了设计要求。设计的无线数据采集系统工作正常。该系统采用自顶向下("Top-Down")的设计方法和自底向上("Botom-Up")的测试方法，采用硬件描述语言进行了RTL级的描述，完成了SPI、I~2C、PWM软核的前端设计。更多还原

【Abstract】 The technology of SoC (System on a Chip) has been a important direction of IC design in21st century. The paper come from mentor’s education department project "Research andDesign IC of the intelligent Information Appliance based on embedded SoC", and mainlystudy and design the SoC soft cores, and design a SoC platform based on 8051 IP. Theplatform verifies the 8051 IP and selects the Wishbone as the interconnection bus between IPcores and MCU. By accessing to the external RAM, it has realized the bridged interfacebetween 8051 and Wishbone by simulation its timing. Meanwhile, expand a external generalI/O port (P4). Design the common interfaces in household electric appliance, SPI, I~2C, PWM,and enhance the performance of 8051 IP. A SoC platform is created successfully, and awireless data acquisition system is built based on this platform.The platform is developed based on the QuartusⅡIntegrating Development Environment,adopt Modelsim 6.2b of MENTOR to simulate the soft cores. The electronic circuit andnetlists requested is obtained by the synthesis tool, Synplify pro 8.1. On the Altera’s CycloneⅡDE2 development board, it expanded AT24C64 chip and PTR8000, and build a testplatform. Through verification, the cores work well and meet the command of system. Thewireless data acquisition system works well, too.The design of system adopts the means of Top-to-Down in front-end design andDown-to-Top in test, and RTL-level code is designed in HDL. The front-end design of I~2C,SPI and PWM soft cores has been completed.更多还原