【作者】 王树起；

【导师】 殷景华；

【作者基本信息】 哈尔滨理工大学 ， 微电子学与固体电子学， 2007， 硕士

【摘要】 随着电子封装微型化、多功能化的发展,三维封装已成为封装技术的发展方向,叠层CSP封装具有封装密度高、信号延迟短、互连性能好等特性,是实现三维封装的重要技术。目前,国外对叠层芯片封装技术研究比较成熟,已开发出八层芯片的层叠封装,但国内大多是以单个芯片封装为研究对象,对叠层CSP封装可靠性的研究却很少。本文采用ANSYS有限元分析方法模拟三层芯片叠层封装工艺流程,分析封装失效机理,通过有限元法预测焊点热循环寿命,并在此基础上对叠层封装进行优化设计,以提高叠层封装可靠性。因此,本研究内容具有重要的理论意义和实际应用前景。本文首先根据封装固化工艺设计三个三维实体模型,通过ANSYS有限元软件模拟分析高温过程三步主要固化工艺,结果表明,在三步主要固化工艺中,最大应力都出现在最底层芯片连接处,底层芯片首先出现开裂和分层现象;比较上述三步固化工艺对叠层CSP封装可靠性的影响,发现第二步固化工艺后,芯片所受应力最大,芯片开裂几率最高,分层现象最明显。基于统一性Anand本构方程,采用非线性有限元方法分析复合SnPb钎料焊点在热循环条件下的应力应变特性,模拟结果显示:高应力和应变区域集中在内侧焊点的角部,这些高应力区域将是裂纹萌生的可能位置。基于上述复合SnPb钎料焊点的应力应变分布的分析,以能量法进行热循环寿命评估,在热循环条件(-55℃～125℃)下,63Sn37Pb钎料焊点热疲劳寿命为685周左右;焊点钎料量相同时,随比值R/r减小,焊点热循环寿命增加,并且随焊点间隙增大,焊点热循环寿命变大。本文采用有限元方法分析SCSP器件的设计参数对封装热应力的影响。模拟结果表明:掺入一定量Cu、Bi或In等金属,无铅材料SnAg系列焊点的可靠性达到SnPb钎料的水平,可以代替含铅材料;芯片所受应力与芯片厚度成反比,底层芯片厚度变化是影响封装体可靠性的主要因素;随着芯片层数增大,芯片所受应力相应增大,当芯片层数超过四层后,随着层数的增加,底层芯片上应力趋于恒定值。更多还原

【Abstract】 With the increasing of multi-function and mini-sized packaging demand, the 3D packaging is becoming a development direction for packaging technology. As stacked chip scale packaging (SCSP) has many good properties, such as higher packaging density, smaller signal delaying and better interconnection, it is one important technique of realizing 3D packaging. At present, the technology of the stacked CSP has become quite mature at abroad, and the 8-dies stacked package has been developed. But in domestic, most of them were mainly concerned about single chip package, and the reliability of the stacked die package was hardly discussed. In this paper, packaging process for a typical stacked three-chip packaging has been simulated to analyse invalidation mechanism by ANSYS finite element analysis (FEA) method. Thermal fatigue character of the solder ball has been studied, and combining FEA results, the stacked package has been optimized. Therefore, it has an important theoretic significance and practical future to study the reliability of stacked die package.Firstly, this paper has designed three 3-dimension curing finite element models to simulate and analyze three major curing processes undergoing high temperature change. The results show that during the each curing process maximum stress occurs in the joints of die the bottom layer, and this may result in die crack and delamination in the bottom layer. By comparing the influence of the curing process on the reliability of the stacked package, it is found that die stress is largest after cureII, and the die is subjected to the highest risk of crack failure and delamination issue is mostly occurred.Based on the unified viscoplastic constitutive Anand equation, nonlinear finite element modeling is used to analyze stress-strain response of 63Sn37Pb solder joint under thermal cycle conditions. The simulation shows that high stress-strain focus in the corner of the inter solder, and crack may begin to grow along the high-stress area.Based on the above stress-strain analysis of the SnPb solder, thermal cycle life was evaluated by the energy. Under the thermal cycle conditions (-40℃～ 125℃), the thermal cycle life of the SnPb solder is about 685 cycles. When solder volumes are same, the thermal cycle life of the SnPb solder increase with the R/r decreasing and solder distance increasing.In this paper, finite element method is applied to analyse the influence of the SCSP device design parameter on the stress of the package. The simulation results show that the reliability of the free-lead SnAg solder adulterated some metals such as Cu, Bi or In etc, is nearly identical to that of the SnPb solder, so free-lead solder can replace the SnPb solder. The stress on dies is negatively proportional to the thickness of die. The thickness change in the bottom layer die is the main factor of the effect on the package reliability. With die-layer number increasing, stress on the dies increase, but the stress in the bottom layer die approximates to constant while using more than four layers in a stacked structure.更多还原