【作者】 刘婷；

【导师】 张民选； 李少青；

【作者基本信息】 国防科学技术大学 ， 软件工程， 2006， 硕士

【摘要】 随着基于IP核复用的SOC设计方法发展,对于可重用IP核的需求越来越大。静态随机存取存储器SRAM以其低功耗的特点已成为微处理器和众多电子产品最常用的存储类部件。而编译器实现的SRAM已经不能满足设计需求,需要采用全定制的方法设计高速低功耗的SRAM存储器。全定制设计开销大,要求所设计的全定制模块具有一定的可配置性和可重用性,从而节省设计代价。因此,研究和设计具有可配置性的SRAM IP核具有重要的应用价值和实践意义。本文采用全定制设计方法,在0.18μm CMOS工艺下设计实现了一款16Kb的SRAM IP核,完成了从逻辑设计、版图设计、内建自测试设计到投片验证以及最终IP化的完整设计流程。该SRAM实现了本文所提出的一种可配置译码结构,不需要改变整个硬核设计,就能实现64位和128位两种位宽的数据读写。这种可配置输入输出数据位宽的设计思想对于编译器的设计具有很好的指导作用。此外,本文还研究了一种具有低功耗特点,基于H树结构的编译器容量扩展方法,并优化设计了一种电流模式的敏感放大器,它的功耗仅为普通Latch结构功耗的77%。在典型条件下,本文所设计的SRAM写入延迟小于1.35ns,读出延迟小于1.54ns,在500MHz频率下,平均功耗为35.053mW,与同等工艺下编译器生成的SRAM相比,访问时间减小了10%,平均功耗减小了20%。更多还原

【Abstract】 With the development of SOC design method based on IP core,the need of reconfigurable IP core increases.Because SRAM comes up low power characteristic, Static Random Access Memory is the most common and important memory component in CPU and other electronic products.At present,SRAM complier can generate different capacity SRAM conveniently and quickly,but its performance can’t reach high-speed and low-power goal in high performance microprocessor.So,it is significant to design a low power and high speed SRAM by full custom design method.For reducing design cost,the designed circuit module with reconfigurable characteristic is necessary.The proposed 16Kb SRAM IP core with reconfigurable input and output data bitwidth is implemented in 0.18μm CMOS process.The structure design,circuit design, layout design,BIST design and IP modeling of IP core are finished,at the same time, the SRAM after taping out is verified.This SRAM with proposed reconfigurable decoder structure can input and output 64 bits and 128 bits data width without changing the design.The design idea guide SRAM complier design.Besides,this paper researches on low power design method of SRAM complier which is based on H-tree structure and optimizes a kind of current mode amplifier,its power consumption is only 77%of Latch structure amplifier’s.In typical case that the work power supply is 1.8v,the delay of writing data in SRAM is less than 1.35ns and the delay of reading data is less than 1.54ns,Under the condition of 500MHZ clock frequency,the average power consumption is 35.053mw. Comparing to the SRAM generated by the memory compiler in the same process,the designed SRAM’s average power consumption reduces by 20%,and the access time reduces by 10%.更多还原