【作者】 李兆亮；

【导师】 刑座程；

【作者基本信息】 国防科学技术大学 ， 软件工程， 2006， 硕士

【摘要】 运算部件作为数据通路的重要组成部分,是数字信号处理器的核心,对芯片的性能、面积和功耗都有很重要的影响。本文的主要目的就是探讨如何对运算部件进行优化设计。在“银河飞腾”DSP芯片中,针对ALU运算单元的定点和浮点指令的运算过程,提出以下优化方案,对其第一站的一个41位加法器、第二站的一个56位移位器和第三站的一个56位移位器采用全定制方法设计。在41位加法器设计中,研究了各种快速加法器的算法,采用速度最快的K-S算法进行全定制逻辑设计和版图设计。对版图提取寄生参数网表通过SPICE模拟结果表明,典型条件下,关键路径延迟0.955ns,面积12280μm~2。在56位桶形移位器设计中,在比较了各种译码移位方式之后,采用了速度较快,传输较稳定的2级3-8混合译码的结构。采用单传输管作为移位阵列,无源阵列大幅度节省了功耗。对版图提取寄生参数网表通过SPICE模拟结果表明,典型条件下,关键路径延迟(译码到数据输出)0.734ns,面积8152μm~2。本文还针对两个全定制设计模块提出完整的流片测试方案,采用扫描测试的方法借助FPGA-PCB板,使用最小的硬件成本进行功能和性能上的测试。此外还对全定制模块建立视图,嵌入到ALU运算单元中进行综合并且进行物理设计。采用了全定制模块设计在三个流水站上的时序都有0.3ns左右的提高,很好地达到了优化目的。设计过程表明,采用全定制和半定制相结合的设计比单纯的半定制设计在时序、面积和功耗上都有明显的改进。更多还原

【Abstract】 Operation unit as an important part of datapaths, is the core of DSP, has great influence on chip’s performance, area and power consumption. The aim of this dissertation is to discuss how to optimize the operation units.Due to the process of L unit’s pointing and floating operation in "YHFT"-DSP, full-custom designing method is introduced to optimize the design of ALU units. The optimization parts are composed of the first stage’s 41-bit adder, the second stage’s 56-bit shifter and the third stage’s 56-bit shifter.In the design of adder, base on the studying of many fast adder, we adopt K-S tree which is the most fast adder algorithm. After the logic design and layout design, simulate the R/C extraction data with Hspice. In the typical condition, the longest delay is 0.955ns, the area is 12280μm~2.In the design of barrel shifter, comparing with kinds of decode and shifte structure, we take the 2 stage hybrid-decoding method that has fast speed and good stabilization. Nmos-only shifter array can reduce power consumption saliently. Simulate the R/C extraction data with Hspice. In the typical condition, the longest delay(from decode to out) is 0.734ns, the area is 8152μm~2.An entire test process after manufacturing has been discussed in the dissertation. Depending up on FPGA, we could easily test the chip’s function and capability(speed) with scan test method. Furthermore, we set the view of full-custom module. Then, embed them in the whole semi-custom design flow from synthesis to detailed route. As a result, the three stages have about 0.3ns’s improvement in timing. It is clear that the combination of full-custom and semi-custom design is more excellent in performance, area and power consumption than pure semi-custom design.更多还原