【作者】 王小强；

【导师】 秦水介；

【作者基本信息】 贵州大学 ， 微电子学与固体电子学， 2007， 硕士

【摘要】 随着宽带网提供的网络协议与服务业务种类的增加，网络处理器已经成为新一代网络交换机与路由器的核心设备。网络处理器一般采用多内核结构和专用指令集处理器技术，具有高性能和灵活性强的优点。MAC层处理单元是网络处理器重要的网络接口单元，负责网络处理器和外部物理层链路的交换，其性能直接影响着网络处理器的整体性能。本文结合网络处理器的研究项目，从实现具有通用总线接口的MAC层处理单元入手，完成了网络处理器以太网MAC层的RTL级硬件实现。本文首先研究了IEEE 802.3标准规定的MAC子层协议，分析了以太网MAC帧格式，并且介绍了Wishbone片上总线的4种互连方式、总线周期和接口信号。本文着重研究了MAC层处理单元的体系结构，对MAC层处理单元进行了功能模块的划分。设计MAC层处理单元由接收模块、发送模块、MAC流控模块、寄存器模块、缓冲区模块、Wishbone总线接口和MII接口控制模块7部分组成。使用FIFO单元缓冲MAC与Wishbone总线之间的数据传输。对发送模块、接收模块、缓冲区模块和Wishbone总线接口进行了比较详细的结构设计和功能描述。通过建立测试平台和测试用例，完成了设计的功能仿真和验证，给出了仿真验证结果。验证结果表明，硬件实现符合网络处理器MAC层的要求。本文的创新点在于：实现了具有Wishbone片上总线接口的MAC层处理单元，该MAC层处理单元适用于网络处理器，并具有一定的通用性；详细推导了以太网的并行CRC校验方法；对MAC层处理单元进行了自己的功能模块划分以及RTL级硬件设计。更多还原

【Abstract】 With the increase of protocols and services for broadband networks, Network processor (NP) has become the core of switcher and router. The architecture of NP is generally composed of multicore. And NP commonly uses the ASIP technology. NP has the advantages of high performance and flexibility. The MAC element which exchanges the data between NP and physical layer is the important interface for NP. The performance of the MAC sublayer impacts the I/O performance of network processor greatly. This dissertation researches the design and implementation of Ethernet MAC sublayer, which is incorporated with the project of network processor. In this paper, a MAC element which has standard bus interface and 10Mpbs/100Mbps data transfer rate has been designed on RTL level.This dissertation studies the protocol of the MAC sublayer for IEEE 802.3 standard and then describes different MAC frames’ structures. To introduce four components of the Wishbone interconnection architecture, classic bus cycles and interface signals.This dissertation detailedly studies the architectures of the MAC element. its architecture is composed of receiver module, transmit module, MAC control module, register module, buffer module, Wishbone interface and MII interface module. The MAC element can transmits data with Wishbone interface through FIFO. It detailedly describes the designs and functions of the receiver module, transmit module, buffer module and Wishbone interface. It has completed the function simulation and verification of this design. The verification results show that the design meets the requirement of the MAC sublayer.The contributions of this dissertation are as follows. A MAC element with Wishbone interface which has generality is proposed. The way for parallel CRC algorithm is detailedly presented. The architectures of the MAC element are detailedly designed on RTL level and implemented by Verilog codes.更多还原