均流、连续升压型PFC芯片的分析与设计

【作者】 武振宇；

【导师】 方健；

【作者基本信息】 电子科技大学 ， 微电子学与固体电子学， 2007， 硕士

【摘要】 电力电子技术发展促进了电力电子装置的大量使用,而电力电子装置的大量使用又给电网带来谐波和无功损耗,造成电网污染。功率因数校正(PFC)技术是减小用电设备对电网造成的谐波污染,提高用电效率的一项有力措施。用电设备的功率因数是衡量其性能的一项重要指标,而提高功率因数的最根本和有效的途径就是采用有源功率因数校正技术。随着对用电设备性能指标要求的不断提高,这一技术得到了广泛的实际应用。从本质上来讲,功率因数校正的目的是使用电设备的输入端口对交流电网呈“纯阻性”,保证输入电流和电网电压随时成正比。在交流/直流电源(AC/DC)前端采用PFC电路,可将输出电压提高至高于最大交流线峰值电压的水平。本文根据与某公司的项目合作要求,基于UMC 0.6μm 30V BCD工艺设计了一种升压型有源功率因数校正电路。本电路采用平均电流、连续导通的控制方式。电路主要包括电压误差放大器、增益调制器、电流误差放大器、振荡器、PFC比较器和PFC输出等模块,还包括了大量与PFC工作相关的保护电路,如过压保护(OVP)、过流保护(OCP)及三重故障(Tri-Fault)保护等功能模块。本文所设计的外围应用电路的输出功率500W,输入为频率50Hz,变化范围为90V~264V的交流电,输出直流电压为400V,输出电压纹波峰峰值为12V,开关频率100kHz,温度范围为0~70℃。在110V输入时,效率为93.8%,PF值为0.9957,THD为5.2%,达到了设计指标的要求。本文在对有源功率因数校正控制策略进行分析与比较的基础上,从设计要求的角度出发,提出了整体电路的架构设计,并设计了500W有源功率因数校正的整体应用电路,完成外围电路元器件参数的设计;根据整体电路的功能要求完成了7.5V参考电压模块、电流误差放大器、振荡器、电流限制模块、PFC比较器、PFC输出及VINOK模块、占空比限制模块、CLOCK输出子模块的设计和仿真。最后,对整体电路的功能和典型性能参数进行了仿真验证和分析。本文在电路原理分析的基础上,运用Hspice对各个子电路模块和整体电路进行了功能和指标仿真,结果均达到预定指标,验证了理论分析的正确性。更多还原

【Abstract】 With the development of power electronics, a bulk of power electronic devices are applied, which brings harmonic and reactive power dissipation to the AC line, called harmonic pollution. Power Factor Correction (PFC) is an effective technique for restraining harmonic pollution and increasing the efficiency of the AC line. The Power Factor of electronic devices is a main index to judging their performance, while Active Power Factor Correction (APFC) is a radical and effective approach to improve Power Factor. With the higher quality requirement of electrical equipment, APFC technique has been widely applied.In essence, the aim of PFC is to make the input terminal of electrical equipment appear resistive to the AC line, and insure that the input current be proportional to the instantaneous line voltage. Employing PFC circuit in the front of the AC/DC power supply can set the output voltage higher than the peak value of the AC line voltage. The thesis is from the cooperation with a company. A boost mode active power factor controller is designed based on UMC 0.6μm 30V BCD technology, which uses average current, continuous conduction mode. The controller mainly contains VEA, GAIN MODULATOR, IEA, OSCILLATOR, PFC COMPARATOR, PFC LOGIC sub-blocks and a lot of protection circuits about PFC operation, such as OVP, OCP, Tri-Fault Detect and so on. The total application circuit proposed has these features: 500W output power, 50Hz line frequency, alternating current from 90V to 264V, 400V output voltage, 12V output voltage ripple, 100kHz switching frequency, 0~70℃temperature rage. With 110V AC input, the circuit has 93.8% efficiency, 0.9957 power factor and 5.2% THD, having achieved the design specification.In this thesis, the control strategies of active power factor correction are analyzed and compared firstly. Then, the whole circuit topology is proposed according to the design specifications. Based on that, a 500W active power factor correction application circuit is designed and parameters of external components are calculated. Based on the whole chip function requirements, design and simulation of sub-blocks are completed, including 7.5V REFERENCE, IEA, OSCILLATOR, PFC ILIMIT, PFC COMPARATOR, PFC LOGIC, VIN OK, DUTY CYCLE LIMIT and CLOCK LOGIC. At last, simulation of whole chip function and some typical performance characteristics are presented.On the basis of circuit principle analysis, sub-block circuits and the whole chip circuit are simulated with Hspice. The simulation results indicate that the circuit has achieved the design specification and the circuit principle analysis has been verified.更多还原