电流模式DC/DC升压控制芯片的设计

【作者】 陆小飞；

【导师】 俞永康；

【作者基本信息】 电子科技大学 ， 微电子学与固体电子学， 2007， 硕士

【摘要】 本文主要介绍了一种用于DC/DC升压变换的控制器的设计。利用HSPICE仿真工具、Cadence集成电路设计环境、采用上华DPDM 0.6um CMOS工艺,根据实际应用的要求完成了对控制器芯片原理及版图的设计,并通过流片得到了最终的芯片。该芯片具有如下基本特性:输入电压的范围为3.0V~5.0V,输出可以在输入电压到10V之间进行调节;采取电流模式的控制方式,具有内部斜坡补偿电路;开关频率设计为500KHz,允许选用小的表面陶瓷电容,可节省板级面积;采用前沿消隐电路(LEB),无须外加低通滤波网络对检测的电流进行处理;具有内部软启动功能,防止启动瞬间的浪涌电流;环路补偿网络外接,增加了灵活性。文中首先分析了电流模式DC/DC升压系统的拓扑结构、基本原理和关键技术,根据这些理论完成芯片整体框架的设计。然后对芯片内部的带隙基准源、振荡器、误差放大器、软启动模块、斜坡补偿模块、PWM比较器、逻辑控制模块、功率管驱动模块等子模块进行了分析并给出了仿真结果。在完成电路原理分析与子电路设计的基础上,对整体电路进行了功能仿真及性能模拟,仿真结果验证了文中阐述的升压型DC/DC转换器的设计理论。接下来介绍了模拟版图设计的有关注意事项,并完成了整体版图的设计。在论文的最后给出了芯片的部分测试结果。本文是电路设计理论与实践相结合的一次很有价值的尝试,为今后设计性能更优的电源管理芯片打下了坚实的基础。更多还原

【Abstract】 In this thesis, a current mode step-up DC/DC controller was presented. The design was based on the CSMC 0.6μm DPDM CMOS process. The EDA tools used in the design include the Cadence custom design platform-Virtuoso, the simulation tool-HSPICE and the verification tool-DRACULA.The controller was designed to generate output voltage as high as 10V with wide input voltage range of 3.0V to 5.0V. High frequency (500kHz) allows easy filtering and faster loop performance. Slope compensation maintains stability at high duty cycle. Soft-start can eliminate the inrush current when controller starts up. The embedded LEB(Leading Edge Blanking circuits) avoids the extra blank circuit. This controller can operate in the temperature rage of -25℃to 85℃.In this thesis, basic principles and some key points of a current mode DC/DC converter were given firstly. Then, the whole chip diagram was proposed and the whole chip operational principle was introduced. Based on the whole chip function requirements, sub-block design and simulation were completed, including bandgap voltage reference, error amplifier,oscillator, slope compensation, PWM comparator, control logic and driver. Then the whole chip function simulation and typical performance characteristics simulation were presented. The thesis also introduces the full custom layout design of some key modules and the whole chip. The whole chip occupies 1715x1331um2. The controller is taped out via MPW in CSMC. The test of the whole system is still in hand.The thesis is a production of circuit principles and practice. This effort accumulates more experience to design step-up DC/DC controller with more perfect performance for the future.更多还原