DVB-S信道解码技术的研究与实现

【作者】 胡海宇；

【导师】 于鸿洋；

【作者基本信息】 电子科技大学 ， 信号与信息处理， 2007， 硕士

【摘要】 欧洲广播联盟提出的数字视频广播标准即DVB系列标准,融合了先进的信息处理技术,得到了许多国家的支持。我国采用数字卫星电视广播标准,即DVB-S作为国家标准。作为数字卫星电视接收机的重要组成部分,现今市场上多数的DVB-S信道解码芯片除了信道解码功能外,并不具备误码统计能力,其它芯片如ST0299,虽然能输出误码统计数值,但是其不足之处是只能通过配置寄存器,每次输出某一种误码统计数据,不能同时输出多种数据。本文研究实现了集信道解码功能和误码监测功能于一身的DVB-S信道解码FPGA芯片,该芯片能够在不中断数字视频广播通信的前提下对信道质量进行监测评估,同时输出四种不同的误码统计数据。论文主要研究了DVB-S信道解码技术中卷积码的维特比解码、解卷积交织、里德-所罗门(204,188)解码和解随机化等各个环节的理论基础和硬件实现方法,重点研究了维特比解码和里德-所罗门(204,188)解码的FPGA设计实现:引入了基于软件流水线技术的回溯法来实现维特比解码器中的幸存路径管理电路,与利用寄存器交换法实现的维特比解码器相比,该算法大大减少了硬件资源消耗,与利用一般回溯法实现的维特比解码器相比,又极大的提高了解码速度,满足DVB-S解码系统实时解码的要求;采用了基于线性反馈移位寄存器的Berlekamp-Massey迭代算法实现里德-所罗门(204,188)解码器中的关键电路计算,从而大大降低了电路复杂度。并设计了一种全新的并行输入并行输出的解随机化电路,从而简化了操作步骤,避免了异步时钟域的出现,减少了系统潜在的不稳定因素。在完成以上工作的基础上,本文设计实现了可以同时输出4种误码统计数据的误码监测器。整个DVB-S信道解码器各个模块的RTL级代码用Verilog HDL编写,并在Xilinx公司的XC2VP30芯片上通过了综合后的仿真验证,整个解码系统在综合实现后通过了板级验证。更多还原

【Abstract】 The standards for Digital Video Broadcasting are produced by the European Broadcasting Union. They are supported by many countries. DVB-S, the standard for Digital Video Broadcast over Satellite, is adopted as the national standard in China. DVB-S FEC chip is the important part of DVB-S receiver. Some of these DVB-S FEC chips are only integrated with FEC decoding function and can’t evaluate channel’s quality. Other chips like ST0299 though have ability to output statistical data of error codes, they can only output one kind of statistical data at a time. This dissertation accomplishes the research and implementation of DVB-S FEC decoder integrated with error monitor, which can evaluate channel’s quality and output four different kinds of statistical data of error codes while decoding is performing.In this dissertation, basic theories and specific implementation methods of Viterbi decoder, de-interleaver, RS (204,188) decoder and de-scrambler are discussed. Viterbi decoder and RS (204,188) decoder are focused on. Trace back algorithm based on software pipelining is introduced to implement the survivor path management of Viterbi decoder, which reduces resource consumption of the design and speeds up the decoding. Berlekamp-Massey iterative algorithm based on linear feedback shift register(LFSR)is adopted to reduce the complexity of RS (204,188) decoder circuit. An error monitor is designed finally, which can output four different kinds of statistical data of error codes at a time.All modules’RTL codes are written in Verilog HDL, synthesized and verified on Xilinx’s XC2VP30. The entire system is online analyzed by ChipScope Pro and the outcome is correct.更多还原