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JTAG的设计与研究

Design and Research of JTAG

【作者】 吕彩霞

【导师】 李哲英;

【作者基本信息】 北京交通大学 , 微电子学与固体电子学, 2006, 硕士

【摘要】 边界扫描技术是符合IEEE规范的一种测试方法,JTAG设计的实现降低了测试的复杂度、提高了质量及缩短面市时间。适合进行超大规模集成电路的测试。同时,JTAG以采用更小的体积而提供更强的功能的优势,主要应用到集成电路设计和测试验证的开发研究方面,但实现边界扫描技术需要超出7%的附加芯片面积,同时增加了连线数目,且工作速度有所下降,这些问题有待解决。本文通过对JTAG标准和技术内容的研究,对JTAG在SoC器件中的应用结构进行了分析,提出了相应的简化措施,以此为据,设计了可用于芯片测试的嵌入式JTAG模块(IP软核),所设计的JTAG模块具有结构简单、技术齐全、支持广泛、测试设计灵活、高精度故障定位等特征,可广泛用于SoC器件的设计。本文通过一定的理论研究,给出了一种实现JTAG结构的具体方法,首次分析了如何选择扫描链的数量与长度的方法与原则,并对测试功耗进行了分析。本文的特点是紧扣IEEE1149.1标准,并对JTAG进行RTL级建模和仿真以及首次对JTAG指令进行了分析,得出JTAG软核的基础测试满足设计要求,并将边界扫描测试设计应用到实际电路当中,实现对边界扫描测试理论的验证。经过仿真验证,证明其设计可靠、方案可行,具有很好的实用价值。

【Abstract】 Boundary-scan technique is a testing method of IEEE. Realization of JTAG reduces the complexity of testing, and increases time to market, thus it is suitable for testing of VLSI. Meanwhile, due to stronger function with smaller volume, mainly used in research on IC design and verification, but to realise bounsary-scan will requires7% extra area, increase the number of lines, and decrease the operating speed. All these problems are to be solved.According to research on JTAG standard and technology conception, the JTAG application architecture in SoC device is analyzed, a simplyfied measure is proposed. Based on this, embeded JTAG IP core which is applicable in chip testing is designed. The JTAG IP core has the following features: simple structure, mature in technique, widely supportive, variable testing method design, high precision error location, and it is widely used in SoC design.Through academic research, detailed method of JTAG realization is presented, and for the first time, how to select the number and length of scan chain and testing dissipation are analyzed. The paper is closely attached to IEEE1149.1 standard, and the novel idea lies in the fact that after analysis on JTAG instruction and RTL level modeling and simulation of JTAG, the fundamental part in JTAG testing follows the specification, boundary-scan testing is applied to actual circuits, and finally the theory of boundary-scan is verified. Through simulation and verification, the reliability and feasibility are satisfactory, and it is of good value.

【关键词】 JTAGSoC器件边界扫描测试
【Key words】 JTAGSoC deviceBoundary-scan testing
  • 【分类号】TN402
  • 【被引频次】16
  • 【下载频次】946
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