【作者】 王韬；

【导师】 余宁梅；

【作者基本信息】 西安理工大学 ， 电路与系统， 2007， 硕士

【摘要】 超宽带通信(UWB)是近年来通信领域兴起的一种新无线互连技术。在UWB的发展过程中，存在两种主流技术方案：基于正交频分复用(OFDM)技术的MBOA和直接序列UWB(DS-UWB)。目前DS-UWB理论已经比较成熟，所以电路实现DS-UWB已经成为一种趋势。本文是基于DS-UWB对基带组帧的电路实现进行的研究。基带组帧在通信系统中有着非常重要的地位，它在发送端对数据进行信源编码、信道编码、交织等处理，使得在接收端可以准确的还原数据。本文首先对基带组帧系统的处理对象基带帧进行了详细的介绍。介绍了帧的各个部分，以及每个部分所代表的内容。其次，详细分析了扰码、卷积编码和交织的原理及算法，并从实时性和结构复杂度方面对几种交织方式进行比较，确定了卷积交织方式。同时根据IEEE 802.15.3a协议，确定了组帧系统的设计方案：扰码、(2，1，6)卷积编码和(7×10)卷积交织。根据这个方案，在MATLAB上搭建了组帧系统和解帧系统。为了直观的显示结果，用512×512像素的lenna图做为输入数据，经过组帧和解帧系统后，还原出来的数据和原始数据进行比较。两者一致证明了系统算法设计正确。接着，根据IEEE 802.15.3a协议和FREESCALE的XS110系列芯片中的MC270123数据手册，完成了组帧系统和Ⅻ接口的电路设计。设计使用Verilog HDL描述语言，QUARTUSⅡ5.0仿真、综合工具。文中对整个系统及几个主要子模块的工作原理作了介绍，并给出了各个模块的仿真结果。文中也对同步FIFO和异步FIFO进行了电路设计，电路在QUARTUSⅡ5.0环境下进行综合、布局布线和后仿，并在写时钟20ns，读时钟40ns的情况下对深度为16的异步FIFO作了FPGA验证。证明异步FIFO设计正确。最后，设计了系统的测试电路，在CycloneⅡ可编程逻辑阵列中对整个系统进行了验证测试。在20ns系统时钟下，输入确定的4000比特数据，同时把这4000比特数据用MATLAB进行组帧，把电路运行的结果跟MATLAB的结果进行比较。两种方法的结果一致，表明设计的电路正确。更多还原

【Abstract】 UWB is a new wireless communication technology in recent years. During the development of UWB,there are mainly two groups MBOA with the key techonology OFDM and DS-UWB competing for the standard.Circuit realization is possible as the theory of DS-UWB is mature. The reaserch in this paper is on ciruit design of system constructing frame in base-band of DS-UWB.This system takes a very important position in communication system. The system mainly including three modules source encode,channel encode and interleaver can be used to ensure the data correctly recovered in destination.At first, this paper introduces the frame of baseband in detail. The introduction contains the structure of the frame and what each part means.Secondly, analyzes the arithmetic of these three modules scrambler、 convolution encode and interleaver detailedly.Besides, this paper compares convolution interleaver with other two interleaver ways in aspect of real time and the complexity of the circuit structure, and chooses the convolution interleaver in the end. According to the protocol IEEE 802.15.3a, this paper confirms the design scheme of system constructing frame in base-band scrambler,convolution encode with parameter (2,1,6) and convolution interleaver with parameter 7x10. The platform of system constructing frame in baseband is constructed in MATLAB in this paper, and also the platform of the system revivification the baseband frame for test. The data from 512x512 picture lenna is as the system’s input data so the result can be shown directly. The data goes through the system constructing frame in baseband and the system revivification the baseband frame, and the data got in destination are as same as the source data. So the system’s function design is correct.Thirdly, According to the protocol IEEE 802.15.3a and data sheet of MC270123 in XS110chip series from Freescale, this paper designs the constructing frame in baseband system and XII interface between MC270123 and MC270143.The system’s circuit is described in verilog HDL, synthsised and simulated by QUARTUS II 5.0 . There are introductions about the system’s and submodules’ working principle in this paper. In this paper, the simulation result of each module is given. Besides, this paper has research on synchronous FIFO and asynchronous FIFO. The asynchronous FIFO with depth 16 words is validated on FPGA, at the situation of the period of writing clock 20ns and the period of reading clock 40ns. The result is given in picture in this paper.At last, this paper constructs the test system for the whole system and validates it on FPGA in series of cyclone II. The test system whose input is 4000 bits fixed data works in the clock with the period of 20ns.simultaneously ,the 4000 bits fixed data are processed by the system constructing frame in base-band in MATLAB. Comparing the output of circuit test system with the result in MATLAB shows they are same. So the system’s circuit design can work correctly.更多还原