【作者】 刘阳美；

【导师】 余宁梅；

【作者基本信息】 西安理工大学 ， 电路与系统， 2007， 硕士

【摘要】 超宽带(UWB)是一种采用ns级脉冲信号宽度、占用GHz级信号频谱、发送功率极低、适用于短距离的无线通信技术。以高分辨率、高截获率、信息含量大和能探测隐蔽目标等优点而成为无线通信领域研究和开发的一个热点。由于超宽带信号发射功率低、信息含量大，容易受到各种干扰，因此降低数据传输的误码率，提高通信的抗干扰能力是一个关键问题，通常采用信道编码来提高通信系统信息传输的可靠性。UWB系统采用IEEE 802．15．3协议，它规定了信息传输的差错控制方案是(2，1，6)卷积码和最大似然的Viterbi译码方案。本文首先介绍了超宽带通信的基本概念和国内外发展动态。针对超宽带信道的特点，采用了经典的纠错码方案，即卷积码和Viterbi译码，并且分析了Viterbi译码器的纠错性能和FPGA设计方案。其次，参照IEEE 802．15．3协议标准，设计了(2，1，6)卷积码Viterbi译码器，采用串行方式进行回溯译码，利用双口RAM存储路径度量和幸存信息。电路使用Verilog HDL语言进行描述，ModelSim软件进行功能仿真，QuartusⅡ软件进行布局布线后仿真，Matlab软件平台产生测试所需要的软判决信息，存储到内部ROM中，解决了软判决信息难以产生的问题，使用逻辑分析仪观测了电路波形，文中给出了仿真波形。最后，在Altera公司的CycloneⅡ系列FPGA上验证了Viterbi译码器电路功能，验证结果表明，电路功能正确，系统时钟44MHz，满足了时序要求，比并行方式节约了大约75％的硬件资源。更多还原

【Abstract】 Being a wireless radio communication technology suitable for short distance communication, UWB (Ultra-Wide Band) adapts ns pulse signal width with GHz signal frequency spectral and lower signal power. It becomes a hot point in the wireless radio communication area for its high distinguishability, high intercepting ratio, more information content and detection ability on concealment. It is a key point to lower the error rate of transmission data in order to improve the reliability of communication. UWB system adapts the IEEE 802.15.3 protocol which employs a (2,1,6) convolutional encoder and maximum likelihood Viterbi decoder in channel coding scheme when transmiting signal data.Firstly, the basic concept and development of UWB technology at home and abroad is introduced in the thesis. Specifically for the channel characteristic of UWB, traditional error correct scheme convoluntional coding and Viterbi decoding is adopted, error correct capability and FPGA design is analysed.Secondly, consulting IEEE 802.15.3 protocol, a (2,1,6) convolutional encoder and its Viterbi decoder is implemented, applying serial mode, trace back decoding, dual RAM storing path metric and surviving information to fufil timing requirement. The circuit is described by Verilog Hardware Description Language, front simulated in Modelsim and after planning and routing synthesized in Quartus II. Soft decision information generated from Matlab simulation platform resolves the difficulty of generating it.The thesis shows the simulation results of modules.Finally, the (2,1,6) Viterbi decoder circuit is verified in Cyclone II FPGA, the result shows that it works well and its system clock frequency is 44 Hz fufiling the requirement of UWB channel coding. Compared with parallel mode, this scheme saves about 75% resource.更多还原