【作者】 王定；

【导师】 余宁梅；

【作者基本信息】 西安理工大学 ， 微电子学与固体电子学， 2007， 硕士

【摘要】 数字音频广播（DAB）作为第三代广播传输模式，具有比传统的模拟广播更突出的优点。为了达到性能更高的音质和数字业务，全数字FM IBOC DAB系统在近年来成为研究的热点。本文首先在分析IBOC DAB系统核心技术的基础上，搭建了适用于全数字FM广播系统的带内同频道基带传输软件仿真平台，在分析比较了多种信道纠错、调制方式和信道估计的前提下，应用误比特率和主观音频质量的对应关系，并综合考虑实现复杂度和运算量，对系统性能进行了快速评定，还讨论了同步和提高仿真速度的方法。仿真结果表明，对于城市拓扑和乡村拓扑环境，采用332ms交织深度、缩减RS码和1／2码率的删余卷积码构成的串行级联卷积码、16QAM调制及1／32保护时隙的系统方案具有优良性能。其次对FFT中关键部分的乘法器进行了优化设计，采用改进的基-4 BOOTH编码方案，设计了24×24位符号定点并行乘法器。使用FPGA进行验证，并采用特许半导体的0.35μm COMS工艺进行标准单元实现，工作在50MHz，最大延时为18.81ns，面积为13238.74门，功耗为17.51mw。在相同工艺条件下，将这种乘法器与其它方案进行比较，结果表明这种结构是有效的。以此为基础，设计了一种可扩展的低功耗流水线booth乘法器，并进行了RTL级代码覆盖率分析。它通过动态范围检测，可实现4×4位无符号数、8×8和16×16位符号定点数、32×32位浮点数4种模式的乘法操作。在特许半导体的0.35μm CMOS工艺下进行标准单元实现，工作在80MHz，这种乘法器比不可扩展流水线booth乘法器的整体功耗节省了34.8％。最后对IBOC DAB系统发射部分基带电路中的扰码、RS（204，188）编码器、时间交织、删除卷积码、频率交织和16QAM映射单元的进行了设计与验证，并将它们进行了集成，利用256×256像素的Lena灰度图象作为测试数据，在Matlab验证平台上进行了验证。结果显示，接收误码率为8.524×10^-5，满足系统要求；在urban fast信道模型下，加入信噪比（SNR）为18db的高斯白噪声，重构图像的峰值信噪比（PSNR）为35.32，证明系统集成模块性能优良。更多还原

【Abstract】 Digital audio broadcast system （DAB） is the third wireless radio system, it have more excellent advantages than traditional AM. Because of pursuing good quality of sound and digital operations, all digital FM IBOC DAB has become an interesting topic recent years.First, based on discussion the key technology of IBOC DAB system, a software platform which simulates a in-band on-channel baseband transmission for the all digital FM radio system is done. After comparing and analyzing kinds of channel corrected, modulation and channel estimation, and utilizing correlation of bit error ratio and subjective audio quality and considering the realization complexity and computation, Rapid assessment of system capacity could be performed, synchronization and accelerate the simulation is also discussed. The simulation results show that the scheme with time interleaving depth of 332ms for Serial Concatenated Convolutional Code （SCCC）、16QAM modulation and 1/32 guard interval duration could get better capacity.Then, This paper presents a low power and high-speed 24×24-b multiplier with modified booth encoder. For low power design, it uses the operator isolation and clock gating glitch free. This multiplier has been verified in FPGA and implemented in chartered 0.35 micron CMOS standard cell technology, with its frequency being 50MHz and its area 14329.74 gates, power 24.69 mw. This architecture is compared with some other architectures using the same technology, and the result shows that it is effective and efficient. Furthermore, a design of low power scalable pipelined booth multiplier with modified booth encoder for ASIC is designed, and RTL codes coverage analysis is completed.The multiplier detects the input operands for their dynamic range and accordingly implements a 4x4 bit unsigned, 8×8 bit and 16×16 bit signed fixed point, 32×32 bit floating point multiplication operation. The multiplication mode is determined by the dynamic range detection unit, which generates and dispatches the control signals for the latched-based pipeline stages. It has been implemented in chartered 0.35 micron CMOS standard cell technology. With its frequency being 80MHz, the proposed scalablepipelined booth multiplier proves to be globally 34.8% more power efficient than a non-scalable pipelined booth multiplier, and it has fast speed due to 5 stage pipeline.Finally, the scrambler、RS（204,188） encoder、 time interleaver、 punctured convolutional encoder、 frequency interleaver and 16 QAM mapping circuit is designed , they are also integrated as a single module. Functional verifications indicate correction. Then, integrated module verification is done based on Matlab verification plantform using the 256x256 Lena as testcase. it is showed that the receiver bit error ratio is 8.524×10^-5 which is lower than 10^-4 .in the urban fast channel model, adding gauss white noise for 18 db, the PSNR of Reconstructions of Lena image is 35.32.it is proved integrated module has better performance.更多还原