雷达信号处理通用芯片验证系统的设计与实现

【作者】 宗竹林；

【导师】 贺知明；

【作者基本信息】 电子科技大学 ， 信号与信息处理， 2007， 硕士

【摘要】 雷达信号处理通用芯片是一个内嵌DSP核的，专用于雷达基带信号处理的SOC芯片。由于芯片的功能代码已经初步实现，当前迫切需要的是一个能够验证该代码的硬件系统。为了保证处于设计阶段的雷达信号处理通用芯片功能的正确性，本文从雷达信号处理通用芯片的功能出发，设计了一个基于FPGA和DSP的雷达信号处理通用芯片验证系统。在本文中，首先对雷达信号处理算法的原理进行了分析和仿真，然后将实现这些算法的ASIC代码转换为能在FPGA中实现的FPGA代码，接着根据代码的外部接口的要求对验证系统的设计进行了详细的叙述，最后介绍了整个系统板的调试过程和验证流程。由于对雷达信号处理通用芯片的功能和接口能够准确的把握，该验证系统充分验证了雷达信号处理通用芯片功能的正确性和设计的可行性，为芯片的顺利投片提供了重要依据，也为雷达信号处理通用芯片测试板的设计提供了实践基础。本论文的主要工作有：1．在深入理解雷达信号处理的基本原理的基础上，本文通过Matlab软件对雷达信号处理通用芯片的算法功能进行了仿真(包括回波模拟，脉冲压缩，动目标显示，动目标检测，恒虚警等算法的仿真)；2．完成了雷达信号处理通用芯片ASIC代码向FPGA代码的转换，并在VCS环境下对FPGA代码进行了仿真；3．根据雷达信号处理通用芯片的输入输出接口的时序要求，编写了芯片输入输出信号的时序产生代码和芯片之间的接口驱动代码；4．根据代码所消耗的逻辑资源和通过对雷达信号处理通用芯片接口分析，完成了雷达信号处理通用芯片验证系统方案的提出和原理图的绘制；5．完成了验证系统单元电路的调试和对雷达信号处理通用芯片的验证工作。更多还原

【Abstract】 The general radar signal processing chip embedded a DSP processor is a SOCwhich is specially used for radar baseband signal processing. Because of the verilogcode of the chip has been realized, the verification system which can verify the code isurgent needed.To ensure the correctness of functions of the general radar signal processing chip, averification system based on FPGA and DSP is designed in this dissertation. Firstly, theprinciples and the algorithms of the radar signal processing have been analysed andsimulated. Secondly, the verilog code for ASIC which have the functions of the chip istransferred to the code for FPGA. Thirdly, the design of the verification system isdescribed in detail. At the end of this dissertation, test results of the the verificationsystem is introduced.The main content and work in this dissertation include:1. In the base of deeply understanding the principles of radar signal processing,of which the algorithms have been simulated by Matlab, including echo, pulsecompression, moving target indication, moving target detecting and CFAR.2. The verilog code for ASIC has been converted to its FPGA counterpart whichhas been simulated under VCS.3. According to the number of logical resource comsumption and the interface ofthe general radar signal processing chip, a solution of the radar signalprocessing system verification has been proposed, and the the schematic sheethas been completed.4. According to the timing requirements of I/O ports of the chip, the verilog codefor the signal generation and that for driver have been programmed.5. Debugging of the circuit units and verificating of the radar signal processingchip have been completed.更多还原