【作者】 张佳；

【导师】 龚敏；

【作者基本信息】 四川大学 ， 微电子学与固体电子学， 2006， 硕士

【摘要】 电子系统设计已进入片上系统SOC阶段，即在单个硅片上集成各种电路功能模块，包括数字和模拟的模块，以实现完整的系统功能。模数转换器是对自然界中的物理信号进行数字化处理的入口部件，它的性能及制作方式直接影响到进行数字信号处理的物理信号的范围及其处理成本，因此ADC是一个非常重要的单元电路。在相当多的应用场合，ADC与数字部分电路常需共用同一个衬底，周围环境噪声很大，所以尽量避免转换器受到交叉干扰至关重要。此外，从成本及日益增多的可携带式设备考虑，也对模数转换器的芯片面积和功耗提出了严格的要求，同时也要求尽量不进行额外的物理修正，这些无疑都增加了ADC的设计难度。随着应用范围的拓展和对系统性能指标要求的不断提高，发展迅猛的SOC设计对高精度低功耗的ADC需求非常迫切。因而设计更高性能的ADC是一项应持续进行的重要课题。 随着半导体工艺技术的不断提高，ADC围绕着精度和速度两个方而迅速发展，出现了双积分型、闪速型、逐次逼近型、折迭插值型、二阶型、过采样型、流水线型、∑-Δ型、混合型等多种结构。不同结构的ADC的应用领域和优缺点也不完全相同，对于便携式或者电池供电的电子设备，要求比较低的供电电压和功耗，逐次逼近模数转换器具有中等转换速度和精度、小功耗、小面积特点，必然成为首选。本论文设计了一个16位的电荷重分布式逐次逼近模拟数字转换器，完成了以下工作： 1、完成ADC全部的电路设计，并采用Spectre进行电路仿真。该ADC达到的主要性能指标为：在典型的工艺条件下，可达200KSPS的吞吐率，转换精度达16bit，最大耗散功率85mW，输入范围达±10Y，片上集成时钟、2.5V基准和高速并行接口，完全达到了预期的目标。 2、基于德国某生产线的0.6um BiCMOS工艺，完成整个电路的LAYOUT，通过ERC、更多还原

【Abstract】 With the development of circuit design coming into the SOC stage, analog and digital modules must be integrated to implement the function of system. But signals in real world generally are analog signals .Therefore, analog-to-digital converters (ADCs) become key blocks in the mixed signal system.Different types of ADC have their own characteristics. Owning to the properties of low power consumption and a small area, the successive approximation register (SAR) ADCs are commonly used for medium-to-high resolution applications such as portable/battery powered instruments, pen digitizers and touch screen controllers. In this work, a 16 bit SAR ADC was designed.To possess the features of fast 16 bit high resolution,- 10V～+10V input range, 100mW max power dissipation, high speed parallel interface etc, new structure of coupling capacitances was adopt to work as ADC’s core module DAC,cause traditional algorithm and structure cannot get the high-precision. Some special designs were also made to realize both high-precision and low power consumption. Charge redistribution technique was employed and a 2.5V bandgap reference, accurate clock were integrated on chip. Compared with many types of reference, at last bandgap reference was used, considering to its best TC and PSRR. A buffer was arranged to follow the reference to increase the load capacity and insulate the noise from the digital circuits. To ensure the clock with the accurate frequency of 5 MHz and duty ratio of 1:1, self detector was added to the clock circuit. Through the state更多还原