【作者】 刘需鸽；

【导师】 唐玉华；

【作者基本信息】 国防科学技术大学 ， 软件工程， 2005， 硕士

【摘要】 网络处理器是路由器中进行报文转发处理的关键部件。由于报文处理具有内在的并行性,网络处理器可采用多种并行技术来加速报文的处理。本文对网络处理器的并行体系结构进行了深入研究,将网络处理器的并行处理分三个层次,分别是PE(Processing Element,处理单元)内部并行,PE间并行和PE与协处理器间并行。由于报文分配策略影响网络处理器并行性能,我们提出了HDW(Hash-based Dynamic Weight)负载分配算法,基于报文流标识与PE间建立映射关系,并将映射关系保存在哈希表中,映射关系基于HRW(Highest Random Weight)算法,增加了负载反馈回路监控PE负载状况,通过动态调整策略阻止PE间负载偏差。模拟结果显示,此算法可以明显的提高PE负载均衡性,减少报文流乱序概率。最后本文在网络处理器原型验证平台上实现网络处理器芯片原型设计。网络处理器芯片原型采用Nios II软核处理器在FPGA上实现,提高了网络处理器的可编程能力。原型系统采用TCAM实现高速路由查找,利用软件实现IPv4报文转发功能。本文实现了Nios II启动微码、报文转发、数据包过滤软件模块设计。更多还原

【Abstract】 Network processors are the key devices to forward packets in the routers. As there is inherent parallelism in the packets processing, network processors adopt many parallel technologies to accelerate the processing of the packets. The parallel architectures of the network processors are explored in this article and the parallel technologies adopted by the network processors are divided into three aspects. They are the parallelism inside the PEs(Processing Element), the parallelism between the PEs and the parallelism between PEs and coprocessors. The distribution schemes of packet influence the performance of parallelism.As the scheme of packet distributed influence the performance of parallelism, in this paper, the HDW(Hash-based Dynamic Weight) scheme for allocation packets in network processors is presented. The scheme is building and keeping one mapping relationship between packets’identifier and PEs in a table of hash. The mapping formula is derived from the HRW( highest random weight ) scheme, it is complemented by a feedback control mechanism designed to monitor processor’s utilization. A dynamic extension to the HRW scheme is provided in order to cope with biased traffic patterns. Simulation results indicate that the scheme achieves significant improvements the load balance of processor and minimizes the probability of flow reordering.On the validate platform of network processors, this paper implements the prototype of network processors chip. The prototype designs with soft-core processors of Nios II in FPGA, improves the programmability of network processors. It implements high-speed routing lookup based on TCAM and IPv4 packet forwarding function through software. We have designed and finished the software module development, including boot microcode of Nios II、packet forwarding and filtrating.更多还原