基于FPGA的多信号检测研究与实现

【作者】 陈文静；

【导师】 钟洪声；

【作者基本信息】 电子科技大学 ， 信号与信息处理， 2006， 硕士

【摘要】 数字信号处理相对于模拟信号处理的优越性主要表现在精度高、灵活性强、可靠性好、易于大规模集成及存储等,所以正受到工程界越来越多的关注。电子系统数字化的最大障碍是宽带高速A/D变换器的高速数据流与通用DSP处理能力的不匹配,必须提高接收机的信号处理能力。VLSI技术的快速发展,以及FPGA的广泛应用,为提高接收机的处理能力,解决高速AD与DSP处理能力之间的矛盾提供了一种有效的解决方法。本文利用FPGA技术,设计了具备多信号处理能力的宽带数字接收机实验平台,并在其上提出了数字接收机实现的可行性方法,以及对这些方法的验证。本文的就以下几个方面开展了研究工作:基于FPGA的多信号检测法:比较了短数据条件下各种测频算法的性能,在此基础上提出了一种基于DFT的快速频率检测算法,通过MATLAB仿真,得出测频精度与所需数据点数之间的最佳关系。该算法可同时检测2个信号,能在4dB条件下工作,相比与传统的短数据频率检测算法,提高了数字接收机的抗噪声能力,缩短了接收机的调谐时间。接收机并行结构算法的工程实现:解决了前端采样的高速数据流远远超过后端DSP处理能力的问题。利用多相滤波下变频的并行结构特点,采用高效的广义滤波器将滤波和混频在一步内完成,使滤波器能够以高效的形式实现,节约了硬件资源,减小了累积误差。经过多相滤波下变频处理后的数据,在速率和数量上都有大幅减少,适应了现有通用DSP器件的处理能力的要求。针对短数据快速测频算法与多相滤波下变频的特点,用FPGA搭建了其实验模型,并利用微机PCI接口,对实验目标板进行控制并与其进行数据交换。可以方便灵活对各种实现方法加以验证、比较,给调试带来了方便,可以每个模块单独调试而不用改变硬件结构,使调试效率大大提高。该平台也可用来对其他数字处理算法进行实现性分析与实验。短数据快速测频算法的具体实现:使用并行流水线的设计方法,提高了系统的数据吞吐率,在100MHz的系统时钟下,能够实时处理400MHz~600MHz速率A/D采样的数据,在64点采样,100MHz系统时钟情况下,初次测频占用时间640ns,以后每次测频占用时间缩短到160ns,实时地提供多相滤波下变频所需的载频位置信息,缩短了接收机的调谐时间。更多还原

【Abstract】 With the continuous developments of modern radar technology and anti-electronic technology, the electromagnetic environment hade become more complicated, the transmitted signal’s carrier frequency had become higher, frequency band occupation had become wider, the form of the signal had become more concealment. All of above factors made it crucial to design wideband, digital, multifunctional software electronic reconnaissance equipment. Another important task is to enhance the electronic reconnaissance equipment’s intercept and capture ability, accuracy, and anti-noise capability as while as reduce the response time. At present, the mismatch between the high-speed data flow of the wideband A/D converter and processing capability of the general DSP hinders the digitization of the electronic reconnaissance system most. On the other hand, the fast developments of micro-electronic technology and the wide applications of FPGA made digital circuit design more effective and afford an available method to resolve the mismatch between high-speed A/D converters and DSP chips.This paper’contributions are concentrated in several aspects as shown below: Comparing with several frequency estimation algorisms’performances on the short data condition, A fast Estimation algorism, based on DFT, is raised. The theoretical analysis, performance analysis and simulation results are also given,Bringing out the best relation between the counts of samples and the counts of frequency segments. This algorism can resolve 2 signals at the same time, and it can properly work with a lower SNR. Comparing with other traditional algorisms, the one enhanced the digital receiver’s anti-noise capability and shorted the response time.To resolve the mismatch between high-speed A/D converters and DSP chips, a improvement parallel structure of DDC is put forward, which is based on poly-phase decomposition. Parallel structure of poly-phase decomposition and parallel mixer is applied in the DDC circuit, it solves the bottleneck in mixing and increases the handle speed. The partition of the tuning channel according to the digital mixing sequence, and the DDC by means of decimating first, the low-pass filtering and mixing realize efficiently the down-conversion of the variable carrier frequency band-pass signal.According to the structure of the DDC and the requirement of the frequency更多还原