GPON中FEC编解码器的研究与实现

【作者】 袁强；

【导师】 胡钢；

【作者基本信息】 电子科技大学 ， 通信与信息系统， 2006， 硕士

【摘要】 在现代通信系统中,前向纠错(FEC)得到了广泛的应用。最新的无源光网络GPON就引入了FEC这一功能。GPON中应用FEC可以减小接收端的误码率,增加通信的可靠性。同时,FEC也可以降低对光器件的性能要求,从而节约成本。GPON中的FEC采用RS码的纠错编码方式。本文重点研究了最流行的两种RS解码算法—Berlekamp–Massey算法和Euclidean算法及其各种改进形式。本文利用VLSI设计思想,将算法映射到硬件结构,实现了RS编码器和三款RS解码器。本文基于修正的欧几里德算法(MEA)设计了一种新的硬件解码器实现结构,称其为FPrME(Fully-pipelined recursive modified Euclidean)解码器。它关键路径延时很小,并且为全流水线连续解码工作方式。对比Altera公司最新的IP Core,FPrME解码器在占用芯片资源和工作频率两方面性能都更好。本文的编解码器采用Altera公司的FPGA芯片Stratix GX EP1SGX25DF672C7在系统时钟125MHz的情况下完成了电路板测试。在RS(255,239)硬件编码器/解码器实现的基础上,本文按照GPON协议要求,针对GPON中最高速率2.488Gbps的下行帧,通过设计复杂的操作时序,实现了符合协议规定的32位并行FEC编解码和解扰码电路,并作了仿真。本文实现的RS(255,239)FPrME硬件解码器的性能在国内外具有领先水平。本文给出的并行FEC实现电路完全符合ITU-T标准,具有很大的应用价值。更多还原

【Abstract】 Forward Error Correction(FEC) has been widely used in the modern communication system. FEC is adopted in Gigabit Passive Optical Network(GPON). FEC in the GPON can reduce the error ratio at the receiver and increase the reliability of communication. At the same time, FEC can decrease the requisition for the performance of the optical devices.FEC in the GPON adopts the Reed-Solomon(RS) code. This paper emphasizes on the most popular RS decoding algorithm: Berlekamp–Massey algorithm and Euclidean algorithm, and their improved form. This paper utilizes the VLSI design method to map the algorithms to the hardware architecture, and has realized the RS encoder and three kinds of RS decoders.In this paper, a new architecture of hardware decoder based on the Modified Euclidean Algorithm(MEA) is provided, and it is called the FPrME (Fully-pipelined recursive modified Euclidean)decoder. It’s critical path delay is very little, and it operates in the fully-pipelined continuous decoding manner. Compared to the Altera’s newest IP Core, the FPrME decoder is better in either size or rate. The encoder and decoders in the paper has been tested on the circuit board using the Altera’s FPGA of Stratix GX EP1SGX25DF672C7 with the system clock of 125MHz.Based on the realization of the encoder/decoders, this scheme aims at the highest rate downstream frame, and has realized the parallel FEC circuit and scrambler complying with the protocols and maken a simulation.The FPrME decoder is advanced in the world. The parallel FEC circuit completely conforms to the ITU-T protocols ,and has important practical value.更多还原