【作者】 黄彩霞；

【导师】 张民选；

【作者基本信息】 国防科学技术大学 ， 电子科学与技术， 2004， 硕士

【摘要】 随着微处理器技术迅速发展,当前寄存器技术的管理与使用呈现虚拟化趋势。X微处理器是我们自行研制的、与IA-64体系结构完全兼容的一款高性能微处理器。本文从分析IA-64体系结构入手,具体研究与实现X高性能微处理器的虚拟寄存器技术,并提出一种新颖的基于映射表的寄存器堆栈引擎RSE(Register Stack Engine)技术实现方法。 X高性能微处理器中的虚拟寄存器技术主要包括寄存器重命名和RSE。本文详细介绍X高性能微处理器中寄存器旋转和寄存器堆栈方式实现的寄存器重命名,举例说明寄存器旋转支持的软件流水技术如何克服传统循环展开方法给代码优化带来的弊端,并进一步给出通用、浮点和谓词寄存器重命名逻辑的具体实现。在RSE方面,本文深入分析该技术在物理寄存器和存储器之间转移数据的实现条件与工作过程,给出RSE状态机和功能部件的设计实现。 设计验证是确保功能和时序正确的重要手段。本文在概要介绍常用验证方法的基础上,在两个不同的层次对RSE及寄存器重命名功能部件进行验证:一方面在模块级对它们单独进行测试,另一方面把它们与CPU内核进行集成,在系统级作为整个X高性能微处理器的一部分进行测试。后者是通过比对同一测试码在Ski IA-64硬件模拟器和Verilog-xL逻辑模拟下的不同运行结果实现的。 在Itanium微处理器中,RSE技术得以有效实现,但是一个过程内不再使用的物理寄存器在该过程执行结束之前不能释放。本文提出一种新颖的基于映射表的RSE技术实现方法,它将编号连续的虚拟寄存器映射到非连续的物理寄存器,使过程内的任一物理寄存器只要使用完毕就可以及时释放,从而更加高效地利用寄存器资源。该方法完全兼容于IA-64体系结构,并支持寄存器旋转和软件流水等关键技术。更多还原

【Abstract】 With the rapid development of microprocessor technology, the management and utilization of register technology has taken on a trend of virtualization at present. X microprocessor is a high-performance processor developed by ourself, and completely complatibale with IA-64’s architecture. The paper begins with an analysis of IA-64’s architecture, then concretely researches and implements the virtual register technology in X high-performance microprocessor, and at last presents a novel mapping-table-based implementation method of RSE (register stack engine) technology.The virtual register technology in X high-performance microprocessor mainly includes regiseter renaming and RSE. The paper detailedly introduces two methods of the regiseter renaming in X high-performance microprocessor, respectively implemented through register rotation and register stack, give an example to show how software pipelining supported by register rotation overcomes the disadvantage to code optimization induced by traditional unloop method, and furthermore implements the renaming design of general register, floating point register and predication register. In respect of RSE, the paper thoroughly studys its implementation condition and process for exchanging data between physical registers and memory, gives the actual design implementation of its finite state machine and functional unit.Design verification is one of the main means to insure the correctness of function and timing. After simply introducing many general verification methods, this paper verifies regiseter renaming and RSE functional units at two different levels. On the one hand, the two functional units is separately verified at module level; On the other hand they are integrated into CPU core , then verified as parts of entire X high-performance microprocessor at system level. The latter is implemented through comparing the two different results from Ski IA-64 hardware simulator and Verilog-XL logic simulator.RSE technology has been implemented efficiently in Itanium microprocessor, but a physical register which has been useless in a procedure can not be released until the procedure is over. This paper presents a novel mapping-table-based implementation method of RSE technology, which maps continuous virtual registers to incontinuous physical registers. A physical register may be freed in time only if it is not required any more in a procedure, so that the register resource will be utilized higher efficiently. This method is completely compatible with IA-64’s architecture and supports some important technology such as register rotation and software pipelining.更多还原