【作者】 刘志碧；

【导师】 陈迪平；

【作者基本信息】 湖南大学 ， 微电子学与固体电子学， 2003， 硕士

【摘要】 微电子技术突飞猛进，工艺特征尺寸已减小到0.18微米以下，0.13微米的工艺已经成熟。基于集成电路工艺的提升，代表集成电路发展水平的微处理器也不断的更新换代，性能越来越高。数字信号处理器(DSP)的发展更是如此。目前，16位定点DSP的工作频率最高已经达到600MHz，而处理能力达到每秒48亿次乘累加运算。3G通信时代的到来将会推动DSP的处理能力的进一步的提高。而未来软件无线电技术的发展，将对DSP的性能提出更高的要求。 为了满足对高性能DSP的巨大需求，中科院微电子所承担了国家863计划重大项目“高性能DSP的研究与设计”。作为项目的一部分，我们设计了一款16位定点DSP作为原型，本文将详细介绍该DSP的设计。 在该DSP的设计中，采用4级流水线，在不损失流水线吞吐率的前提下，使流水线的控制相对简单；总线结构采用哈佛结构，能够保证DSP有足够的数据吞吐率，为计算部件提供充分的数据；采用与主流DSP兼容的指令集，以便于后续的开发应用；采用高速的乘累加单元，保证单时钟周期完成一次乘累加运算；采用并行技术，单时钟内完成一次运算和从存储器读取两个操作数；采用“零开销”循环技术，提高循环指令执行的效率；采用延迟转移，提高流水线的吞吐率；采用后变址寻址和位反寻址技术，提高访存指令的效率。在行为级描述上，从数据通路和控制通路两个方面对DSP进行行为建模。在RTL(Register transfer level)设计上，尽量遵守RMM(Reuse methodology manual)规则，以保证代码的可移植性。在功能验证上，采用分层次验证的策略，在模块级采用白盒法进行验证，在顶层采用白盒法与灰盒法相结合验证，采用随机测试矢量与特定测试矢量结合以提高测试覆盖率。采用synopsys公司的综合工具Physical compiler进行综合，采用Astro进行自动布局布线，整个设计的规模约为80万门，时钟达到9ns。更多还原

【Abstract】 As the technology of microelectronics is advancing rapidly, the process technologies with the feature sizes of 0.18um and even 0.13um are widely used in commercial applications. With the development of microelectronics technology, microprocessors including digital signal processor (DSP) which represents the development level of integrated circuits are updated constantly and the processing ability becomes stronger and stronger. Up to now, 16-bit fixed-point DSP with the frequency of 600MHz can deal with 4800 million multiplier and accumulation computation (MAC) on only one second. Especially, the strong requirement for the third generation (3G) mobile communication applications promotes the rapid development of DSP. In near future, the applications based on Software Defined Radio (SDR) technology will need more powerful DSPs.Aiming to meet with the great demands for high performance DSPs, a DSP research project supported by national "863 projects" are being carried out in the Institute of Microelectronics, Chinese Academy of Sciences (IMECAS). As a part of this project, we designed a prototype DSP which is a 16-bit fixed-point DSP. This thesis mainly discusses the design of this DSP.In our DSP design, a four-level pipeline is used when designing the architecture, which predigests the control of pipeline without the loss of performance. The bus architecture modifies the Harvard architecture to provide enough data rate for computing units. The instruction set of DSP in mainstream is used which makes it more convenient for later development based on our DSP. The MAC unit of the DSP is fast enough to accomplish a multiplication and an accumulation in a single cycle. The parallel technology is used so that the DSP can do a computation and get two operands from on-chip memory in a single cycle. Zero-overhead loop is implemented and delay branch is realized to make the pipeline more efficient. Behavioral models are made for data path and control path. We obey the rules of Reuse Methodology Manual when designing on Register-transfer-level to make the codes re-usable. Function verification is done in hierarchy: On module level white-box verification is used and on chip level both white-box and grey-box. To improve coverage rate both random and specific stimulus are created. The area of the whole design is about 800Kgates and the time is 9ns.更多还原