【作者】 何震；

【导师】 曹阳；

【作者基本信息】 武汉大学 ， 通信与信息系统， 2004， 硕士

【摘要】 根据摩尔定理，芯片的集成度每18至24个月翻一倍。集成度的提高使得生产出来的芯片产品面积更小、速度更快。在第三方IP(Intellectual Property)的支持下，微电子学的发展促使了在单一芯片上能够包含多种功能模块，这种芯片就被称为片上系统(System-on-Chip，SoC)。 从专用芯片(Application Specific Integrated Circuit，ASIC)过渡到片上系统，虽然在单一芯片上包含的功能越来越多，但同时对片上系统进行验证所带来的挑战也越来越大。当芯片的规模变得很庞大时，传统的验证方法已经无能为力。在寄存器传输级(Register Transfer Level，RTL)进行验证时，由于使用硬件仿真器所导致的仿真速度很低，且验证耗时很大。此外，由于寄存器传输级验证缺乏对软／硬件并行开发的支持，不利于快速进行软／硬件协同验证。 为了克服传统验证方法的局限性，本文提出了新的SoC验证方法——基于随机测试的SoC系统级验证方法。该方法源于新的验证思想，即在SoC设计的更早期发现更多的功能性设计错误。 论文的开始介绍了SoC系统级验证方法学和有关随机测试的理论，这两方面是进行论文研究的背景知识。新的SoC验证方法是在上述两方面知识的基础上提出的。 在本文的研究中，采用基于SystemC和SCV(SystemC Verification Standard)验证库的方法来创建系统级的测试平台。具体地说，在系统级验证中所使用的测试平台是采用SystemC 2.0描述的，系统级测试平台中测试向量的生成是根据SCV验证库的三种随机化机制：直接随机化、带权重的随机化和带约束的随机化。 新的验证方法可以在SoC系统级验证平台上执行，这一平台是在Sun Blade2000工作站上通过集成编译、连接和调试工具、安装SystemC库和SCV验证库构建而成的。论文中的SoC系统级验证平台是WHU SLD 1.0的一部分，WHUSLD 1.0是在研究SoC软／硬件协同设计和协同验证这一国家863项目过程中开发出来的工具原型。 通过对4×4包交换芯片的系统级模型进行一系列的验证实验，证实了基于随机测试的SoC系统级验证方法是可行的。论文具体阐述了如何创建系统级测试平台、如何对测试平台和被验证对象(Design Under Verification，DUV)进行绑定、如何根据SCV验证库的三种随机测试向量生成方法生成测试激励。针对4×4包交换芯片系统级模型不同方面的功能，论文完成了4个验证实验：通过对实验结果进行分析，反过来对论文中所提出的新的SoC验证方法进行了评估。结论表明，本文提出的验证方法能够有效地完成SoC系统级验证。更多还原

【Abstract】 According to Moore’s Law, the number of transistors per chip doubles every 18 to 24 months. The escalation in gate count has enabled the electronics industry to make major strides in producing smaller and faster consumer and communication products. The development of microelectronics makes these products contain multiple functions on a single IC (Integrated circuit), supported by various custom-designed and third-party Intellectual Property (IP). These single chip systems are called SoC (System-on-Chip).Although the advance from ASIC (Application Specific Integrated Circuit) to SoC can provide more and more functionality for a single chip, it presents enormous verification challenges for SoC designs. The traditional verification methods become less and less powerful as the scale and complexity increase. During RTL (Register Transfer Level) verification, the using of HDL (Hardware Description Language) software simulators has been proven to be inefficient and more time-consuming. In additional, these approaches lack the parallelism needed to rapidly verify the interaction between hardware and software blocks in a SoC design.In order to deal with the above limitations during the conventional verification, a new verification methodology for SoCs, methodology of SoC system level verification based on random testing, is proposed and established in the dissertation. On one hand, the new verification methodology is derived from the criteria: find more functional errors in the earlier SoC design cycles compared with register transfer level. On the other hand, the new verification methodology has deployed a feasible technique that can address the verification bottleneck for SoC design.The methodology of SoC system level verification and the theory of random testing are introduced directly at the start of this dissertation, which are the background for researches in the thesis. In fact, the new SoC verification methodology is brought forward based on knowledge in the above two aspects.Apart from the basic knowledge, the research of creating testbench for system level verification is on the basis of SystemC and SystemC Verification Standard (SCV). Specifically, testbench for system level verification according to the new methodology is described using SystemC 2.0. Moreover, test cases for the system level testbench is generated according to three different mechanisms of randomisation based on SystemC Verification Standard specification, which consist of direct randomisation, weighted randomisation and constrained randomisation typically used in verification.The new verification approach can be implemented on the platform of SoC system level verification, which is constructed by integrating compiling, linking and debugging tools and installing SystemC and SystemC Verification Standard libraries on a Sun Blade 2000 workstation. Actually the platform is a part of WHU SLD 1.0 that is the tool prototype for SoC system level design developed in a National 863 Project about researches on SoC hardware/software co-design and co-verification.The methodology of SoC system level verification based on random testing is demonstrated on a series of experiments, which implement functional verifications on system level models of 4 X 4 package switch. The thesis sets forth in detail how to create system level testbench for the verification, how to bind the testbench and theDesign Under Verification (DUV) and how to generate test stimuli in accordance with three types of randomization in SystemC Verification Standard. Through analysing results of four different experiments that verified different functions provided with the system level model of 4 X 4 package switch, the new verification method put forward in this dissertation has been evaluated contrarily. The results have indicated that the method proposed in the paper can be used to fulfill SoC system level verification efficiently.更多还原