【作者】 张志远；

【导师】 范俊波；

【作者基本信息】 西南交通大学 ， 密码学， 2004， 硕士

【摘要】 USB技术的发展方兴未艾，支持USB协议的设备种类也越来越多。1998年USB1.1协议正式发布，可以支持1.5Mbps和12Mbps两种不同的速率。2000年USB2.0的出现将最高速度惊人的提高了40倍，达到了480Mbps。然而作为一种流行的总线标准，它5米的线缆长度限制始终是一个巨大的障碍。虽然可以通过5个集线器级联的方式将这一距离提高到30米，但在很多情况下仍然不够用。因此开发一种USB延长器具有非常重要的意义。 本文讨论了一种USB延长器的模型。它基于USB1.1协议，在主机侧添加了一个本地扩展LEX，设备侧添加了一个远程扩展REX，两者之间采用普通网线进行连接。同时为了使设备能正常工作，还改写了LEX和REX部分的USB协议。本文首先讨论了USB延长器模型的结构，把模型模块化，介绍了每个模块的功能分工和引脚设计，并给出了一个总体的电路图。然后详细讨论了每个模块的实现，用Verilog HDL语言实现了各个模块的功能，并给出了仿真结果。文章依据USB1.1协议，重点讨论了LEX和REX端协议部分的设计，给出了用Verilog语言实现的源程序和仿真结果。最后文章总结了该方案的优缺点，并提出了进一步完善的思路。更多还原

【Abstract】 USB is a very popular bus standard today, and more and more USB-supported-peripherals have been developed. In 1998, USB 1.1 protocol specification was released, and it could support a low speed of 1.5Mbps and a full speed of 12Mbps. In 2000, USB2.0 was released, and it could support a more high speed of 480Mbps, which was 20 times faster than USB 1.1. But as a popular bus standard, it only supports a 5-meter-long cable. This is a big barrier. Though we can use 5 in series Hubs to prolong it to 30 meters longer, it can’t meet our demand sometimes. So it is a very meaningful work to develop a function to extend the range of USB peripherals.In this thesis, a solution based on USB 1.1 protocol is introduced. A local extend equipment (LEX) is placed at the end of the host, and a remote extend one (REX) at the end of the peripheral, and the two units are interconnected by the category 5 Unshielded Twisted Pair (UTP) cabling. At the same time, we adjusted the USB protocol of LEX and REX, through which the peripheral may work well. Firstly, the architecture of this solution is discussed, then the function and pins design of each block are introduced, and also the entire circuit diagram of the system is shown. Secondly, the implementation of each block is discussed in detail, and the source code in Verilog HDL and the simulation results are also given. Based on USB 1.1, the protocol design for LEX and REX is chiefly discussed, and the source code in Verilog and its simulation results are also given. Finally, advantages and disadvantages of this system are summarized, and possible solutions are put forward.更多还原