【作者】 冯立营；

【导师】 赵晓群； 王霞；

【作者基本信息】 河北工业大学 ， 微电子学与固体电子学， 2004， 硕士

【摘要】 针对第三代IP电话的技术现状和发展趋势，本论文提出了一种新型的嵌入式IP电话终端解决方案，并完成了该终端的核心部分，语音编解码器的设计与实现。 该语音编解码器的硬件基于TMS320VC5410，编解码算法遵循ITU-T G.729A协议，能够实现语音信号的采集/回放、编码/解码以及同嵌入式CPU通信等功能，在8kbit/s的码率下能够提供获得良好的语音质量。 现有的G.729A定点算法大都是针对通用计算机编写的，没有考虑算法的实时性问题。因此需要根据DSP的结构特点，对算法进行优化。在对ITU-T提供的G.729A标准C源代码进行测试时发现，一些单次调用消耗运算量不大的基本运算，往往被调用几千次，消耗了整个算法运算量的90％以上。采用了内联函数和宏语言相结合的方法对这些基本运算进行了优化，优化后G.729A编码器的计算复杂度由530MIPS降低到94MIPS。这一步是整个算法优化的关键。接着，采用DSPLIB库函数对算法中的数字信号处理函数进行了优化，根据DSP的结构特点，改写了部分循环和判断转移语句，最终整个算法的计算复杂度降低到30MIPS，完全满足实时要求。整个优化过程始终着眼于底层函数的优化，没有把主要精力放在固定码本搜索、自适应搜索等单次调用耗时较大的算法上。实践表明，本文提出的自底向上的优化方法，效果良好，优化迅速，对其他算法的优化也有借鉴意义。 提出了“DSP+嵌入式CPU”的IP语音终端解决方案，并给出了IP电话编解码器的系统构架和芯片选型。在电路模块分析中，重点介绍了电源环境的构建、语音信号采集/回放(A/D、D/A)模块的设计、DSP与嵌入式CPU通信接口设计以及DSP核心部分设计，并给出了在原理图设计、制板与调试过程中总结的经验。最后，详细介绍了IP电话编解码器软件的设计，主要有系统自举启动设计、DSP芯片初始化、TLC320AD50C驱动程序设计以及系统软件流程设计等。更多还原

【Abstract】 Based on the analysis of current situation and the development trend of IP phone, this paper has put forward the solution of a kind of new-type embedded IP phone terminal and has finished designing the IP phone codec which is the key part of IP phone terminal.The hardware of the IP phone codec to be designed is based on the fixed point digital signal processor (TI’S TMS320VC5410) while the compression and decompression core in the software of DSP is based on the ITU-T vG.729A .IP phone codec carryout the task of collecting /playing-back .coding /decoding of speech signal and communication with embedded CPU.etc.The existing fixed-point implementation of G.729A is generally written on all-purpose computer, and is no considered real-time quality problems . So the algorithm is needed to be optimized . when testing the G.729A ANSI C source codes offered by ITU-T, we found that some basic operations are called several thousand times and consist of more than 90% of the operation quantity of the whole algorithm.After optimizing these basic operations with the method of combining intrinsic with macro language,the complexity of calculation of G.729A encoders is reduced from 530 MIPSs to 94 MIPSs. This is a key for the optimizing of the whole algorithm . Then,the digital signal processing functions in G.729A are optimized by DSPLIB.According to the structure characteristic of DSP,some sentences of circulation and shifting are rewritten.Finally,the complexity of calculation of the whole algorithm is reduced to 30 MIPSs,which satisfies the real-time request very well.This thesis has put forward IP phone terminal solution of DSP+ embedded CPU ". On the basis of this scheme, this text introuduces the IP telephone systematic framework and the selection of chips for the codec. The circuit design ,focuses on the following hardware modules: power structure environments, A/D,D/A inverter, DSP and embedded CPU’s communication interface,DSP modules,and so on. The problems and the corresponds solutions which found in the design and debug are discussed,too. At last, the software design is presented in detail,including system booting,initialization of DSP registers,drivers for AD converter and system software.更多还原