【作者】 陈瑞琪；

【导师】 侯春萍；

【作者基本信息】 天津大学 ， 通信与信息系统， 2004， 硕士

【摘要】 无线局域网（WLAN, Wireless Local Area Network）是未来移动通信系统的重要组成部分。为了满足用户高速率、方便灵活的接入互联网的需求，WLAN的研究和建设正在世界范围内如火如荼的展开。由于摆脱了有线连接的束缚，无线局域网具有移动性好、成本低和不会出现线缆故障等特点。本文对无线局域网的主流协议IEEE 802.11a的物理层实现技术进行了系统的研究和分析，并采用可编程ASIC器件FPGA，设计实现了物理层基带处理的关键模块，为今后形成具有自主知识产权的IP核奠定了基础。本文研究内容得到了天津市信息化办公室“宽带无线局域网关键技术研究”项目经费的支持。本文在对IEEE 802.11a协议深入研究的基础上，提出了物理层的实现方案和功能模块划分。重点研究了实现基带处理的关键模块：FIR滤波器、卷积码编码器以及(2,1,7)Viterbi译码器的实现算法和硬件结构。在Viterbi译码器的设计中，针对802.11a系统的具体参数，提出了一种采用4个ACS单元并行运算的硬件实现结构；同时从路径度量管理着手，创新合理地组织存储器的结构；并在传统回溯算法的基础上提出了以双回溯算法结构实现回溯过程。理论研究和实验结果均表明，本文所提出的结构具有译码速度快、结构简单、易于实现的优点。本文使用Altera公司的QuartusII开发平台对所设计的基带处理模块进行了功能仿真和时序仿真，结果表明所提出的算法方案和硬件实现结构正确可行。更多还原

【Abstract】 WLAN (Wireless Local Area Network) is the important part of future mobile communications system. In order to meet the need of accessing flexibly the Internet with high rate at great ease, WLAN is being researched and established around the world. WLAN features mobility, low cost and wire line failure free.This project does a lot of research work about IEEE 802.11a, which is the main protocol of WLAN. OFDM system, the Physical Layer in WLAN, is implemented by using FPGA (Field Programmable Gate Array), which is IP (Information Patent) and is prepared for ASIC. This project is supported by the bureau of the Tianjin Information Office’s “The Implementation of The Key Technology in Broadband WLAN”.After carefully studied and analyzed the protocol, we proposed a practical way to realize the Physical Layer in IEEE 802.11a. Lots of efforts have been contributed to the algorithms and architectures of the FIR module and (2,1,7)Viterbi module, which are the key component in 802.11a base-band process. To fit in with the high-speed request of Viterbi decoder in WLAN， a novel parallel architecture of Viterbi decoder is proposed in this paper. The paper also gives the realization approach of how to arrange the architecture of RAM, which focuses on the point of path management, and puts forward a new double trace-back algorithm. And theory study and experiment result prove that the decoder can be structured simply and has higher speed.This paper simulates the FIR module and Viterbi module with QuartusII, the results of function-simulation and timing-simulation both prove the proposed method is right.更多还原