【作者】 吴梦洁；

【导师】 肖立贤；

【作者基本信息】 华北电力大学（北京） ， 计算机应用技术， 2004， 硕士

【摘要】 Cache即高速缓存，是位于CPU和主存之间的规模小速度快的存储器。Cache的工作原理是保存CPU中最常用的数据。当Cache中保存着CPU要读写的数据时，CPU直接访问Cache。由于Cache的速度与CPU相当，CPU能在零等待状态下迅速地实现数据存取。只有在Cache中不含有CPU所需的数据时CPU才去访问主存。Cache在CPU的读取期间依照优化命中原则淘汰和更新数据。可以把Cache看成是主存与CPU之间的缓冲适配器，借助于Cache，可以高效地完成DRAM内存和CPU之间的速度匹配。因此，Cache是当今衡量计算机系统性能的一项重要指标。 为了发展民族的CPU产业，许多专家学者都在致力于研究有自己特色的CPU。北京凝思公司总裁宫敏博士就是其中之一，为了研制基于高端安全服务器的64位通用CPU，宫博士成立了研发队伍，研制LX—1164 CPU芯片。本人有幸在夏宏博士的指导下参加这一工程，承担LX—1164 CPU的高速缓存控制器(CCU)的逻辑设计和功能仿真。 本文介绍了我们所研制的基于安全服务器的64位通用CPU芯片中的快存控制器CCU(Cache Controller Unit)的设计原理和硬件实现。LX—1164 CPU将采用0.18μmCMOS工艺，工作主频为400MHz，安全、可靠、低功耗是其最大的特点。LX—1164具有独立的32KB片内数据高速缓存和32KB片内指令高速缓存，通过CCU可以同时对指令Cache和数据Cache进行查询。CCU采用ASIC的全定制电路设计方法，使用先进的EDA设计工具进行逻辑设计与功能仿真。在设计上突破传统思想的约束，采用可重构技术降低Cache的功耗。所谓可重构技术是指系统中的硬件结构可以根据应用程序的需求进行重新配置。本课题中运用Cache重构技术对Cache的组织结构和数据存储方式进行改进和优化，通过在Cache中设置控制逻辑和选择合适的调整策略对Cache进行重构从而实现对Cache容量的动态调整，同时采用压缩的数据存储方式减少Cache的存取量，从而大大地降低了Cache的动态功耗，附加晶体管的引入又有效地降低了静态功耗，仿真结果证明该技术可有效地降低数据快存和指令快存的功耗，使整个系统性能有所提高。 由于本文涉及凝思公司技术机密，所以有关的技术细节未能详细阐述。敬请评委原谅。更多还原

【Abstract】 Cache memory is a software transparent fast memory layer between the CPU and the main memory. It is so transparent that application developers do not need to think of its existence. Cache memory is constructed with high-speed static random access memory(SRAM), managed in a unit called cache line. The cycle time of SRAM can be as short as a few nanoseconds. This kind of performance can match the speed of microprocessor bus operation. The size of a cache line is usually a few processor words.Although SRAM is fast, it costs too much. A basic DRAM cell uses one transistor while an SRAM cell uses four. With the help of a cache memory all memory access requests,whenever possible, take place in cahce memory;main memory will be referred to only when it is necessary.Since a cache memory system can reduce the need for main memory access, It greatly reduces the potential memory access contention in shared memory Multiprocessor systems. It localizes memory access by isolation CPU bus traffic from memory bus traffic.This paper presents the logic circuit design of CCU for LX-1164 CPU chip, for CCU, data and instructions are stored in separate data and instruction caches. So it allows the processor to fetch instructions from the instruction cache and data from the data cache simultaneously. CCU contain a tag array and a data array. Dividing the cache into separating tag and data arrays reduces the access time of the cache. In order to keep the cache coherence , CCU adopts MOESI protocol.We adopt ASIC design technique, using advanced EDA tools to design and simulate CCU. At the same time, We propose an optimization methodology for power minimization by reconfiguring the organization of cache and changing the form of words stored in some cache lines.As this paper is related to technical secret of the linx company, so I can’t give you information in details,I am so sorry about it.更多还原