八位嵌入式RISC MCU IP核设计研究

【作者】 杨成文；

【导师】 王玮；

【作者基本信息】 西北工业大学 ， 电路与系统， 2004， 硕士

【摘要】 现代信息技术的高速发展使得SOC(片上系统)逐渐成为IC设计的发展趋势。而IP核复用技术由于能大大提高SOC开发效率并降低设计成本逐渐成为一种主流的设计方法。本文的研究课题—八位嵌入式RISC MCU IP核的设计正是对此进行的一次有益的尝试与实践。 本文对PIC16C6X单片机系统结构、指令系统和系统时序进行了分析，并且在此基础上对精简指令集MCU IP核进行顶层功能和结构的定义与划分，建立了一个可行有效的RISC MCU IP核模型 本文将MCU IP核划分为数据通道与控制通道两部分，采用ASIC设计中的高层次设计方法，使用硬件描述语言Verilog HDL对这两部分的各功能模块进行了设计描述；利用多种EDA工具对整个系统进行了仿真验证与综合。更多还原

【Abstract】 With the rapid development of the Information Technology, SOC has become the development trend of IC design. And the methodology based on the IP duplicate technology, which can improve the design efficiency at a large degree and decrease the cost, is becoming the chief methodology of SOC design gradually. The subject of this thesis-An eight bit embedded RISC Microcontroller Unit IP Core design is just a helpful try and practice with this methodology.This paper gives complete analysis for the system architecture instruction set and system time sequence of PIC16C6X one-chip computer. Based on the analysis, the RISC MCU IP soft core’s top function definition and structure partition are finished in this thesis. A effective RISC MCU IP core model has been set up.In this paper, using a top-down design scheme, the RISC MCU IP core is divided into two parts: data path and control path. All the modules in the two parts are described by Verilog HDL, a kind of hardware description language. The simulation and synthesis of the whole work are finished successfully with EDA tools.更多还原