【作者】 梁毅；

【导师】 高勇； 余宁梅；

【作者基本信息】 西安理工大学 ， 微电子学与固体电子学， 2003， 硕士

【摘要】 论文针对目前大规模集成电路设计要求，结合电力电子应用，设计了一个SPWM信号产生系统IP软核，该软核可广泛应用于系统级芯片设计中。 首先，论文通过分析目前集成电路发展现状和PWM技术在电力电子领域的广泛应用，论证了设计全数字三相SPWM信号产生系统IP软核的必要性。 其次，对实现原理和在设计中需要用到的直接数字频率合成技术进行了深入的分析。 再次，按照设计流程，具体实现了该系统。主要步骤包括：系统设计，模块设计，功能仿真。系统设计是基于SPWM的实现算法和设计指标要求，对系统划分模块和对各个模块进行信号连接；模块设计是设计每个模块内部电路结构，并用Verilog语言编写可综合可复用代码；功能仿真使用的工具是CADENCE的NC_Verilog，首先对每个模块进行功能仿真，仿真通过之后，把所有模块代码组合在一起，构成整个系统代码，在外部输入端口加激励，对整个系统进行功能仿真。同时，在这部分还对可复用可综合代码的编写做了比较深入地研究与探讨。西安理}_人学硕十学位论文 最后，用FPGA对系统进行了功能验证。使用X工L工NX的FI，GAXC255OPQZOS芯片，经过FPGA的实现流程，把配置文件配置到芯片中。搭建了一个验证系统，通过单片机来配置初始化寄存器和控制寄存器的值来控制系统的工作状态，用逻辑分析仪采集输出的信号。功能验证的结果表唠本设计完全实现了设计所规定的指标。更多还原

【Abstract】 According to the requirement of the VLSI and the wide application of power electronics, IP soft core of SPWM generation system is designed. And it can be widely applied in system level chip design.Firstly, the necessity of designing the full digital three-phase SPWM signal generation system is discussed by analyzing the actuality of the IC development and the application of the PWM technology in power electronics.Secondly, the principle and Direct Digital Frequency Synthesis (DDS) is analyzed deeply.Thirdly, the whole system is designed according to the design flow. The main process includes following: system design, module design and function stimulation. The whole system is divided into several modules and each module is connected by signals, which based on the arithmetic of SPWM and the requirement of design. The module design is to design inner circuit structure of each module and uses Verilog language to code the synthesizable and reusable code. The functional stimulation uses the NC-Verilog of Cadence. First, each module is simulated. Then, after the right result comes out, the code of each module is assembled to form the code of whole system. Last, the simulation signal is applied on outer port to simulate the whole system. Together, in this part coding the reusable and synthesizable code was deeply discussed.Lastly, FPGA is used to test the function of the system. The FPGA chip used isXC2S50PQ208 of Xilinx. The configure file is downloaded into the FPGA chip according to the FPGA design flow. Also a test system is set up, and the work status of the system is controlled by single chip to download the data of initial registers and control registesr. And the logical analyzer is used to sampling the output signals. The results of function test show that the design accomplished the requirements perfectly.更多还原