高速帧同步格式化器

【作者】 苏向东；

【导师】 杨晓波； 谢澍霖；

【作者基本信息】 电子科技大学 ， 电路与系统， 2003， 硕士

【摘要】 高速数据传输处理技术是现代通信系统研究的主要新热点方向之一。随着数据传输速率增高，其帧同步的实现就越来越困难，而该领域主要是应用高速数字电路技术。基于此，本论文试图解决其在空间卫星通信上的应用－“高速帧同步格式化器”的实现。高速帧同步格式化器是遥感卫星地面接收系统中必不可少的关键设备之一，主要将从卫星接收到的高速数码流格式化，使计算机得以辨识每一帧的起始位置，然后将数码流经高速接口进入计算机进行预处理。现代军事和民用对地观察卫星的分辨力越来越高，因此对地面站系统的性能的要求也越来越高，而对作为卫星地面站的核心关键之一的帧同步格式化器的要求当然也是越来越高，不仅对速率的要求提高了很多，还要求其能应用于多种卫星。高速帧同步格式化器的国外报价昂贵，并且军用卫星数据格式及加密都为国家机密，所以不可能都购买国外的产品，必须国产化。这一工作的完成，将在这个关键环节上有助于我国新型遥感卫星、军用卫星地面系统的建设，促进我国遥感卫星应用技术的发展。本文主要完成了高速帧同步格式化的设计方法、仿真及其软硬件实现。该高速帧同步格式化器最高工作速率为150Mbps，适用于多颗卫星多种帧格式，可通过计算机初始化控制。其可控参数有：IQ路信息、帧头长度、帧同步码内容、帧同步误差容限（同步门限）、帧保护容限（锁定门限）、帧保护系数（失锁门限）、帧的长度。为完成设计指标，作者查阅了大量相关资料，同时完成了：FPGA编程实现主体设计、系统的仿真、制作高速PCB板、编写单片机控制程序、调试实验。实验结果表明，高速帧同步格式化器的设计达到了速率高，控制灵活的要求。更多还原

【Abstract】 High-speed data transfer technique is one of the key hotspot aspects in modern communication system. It becomes more difficult to realize frame synchronization with higher data transfer speed, and this field applies mostly high-speed digital circuits technique. So this dissertation named "High-Speed Frame-Synchronizer" tries to resolve the application of high-speed digital circuit technique in satellite communication. High-Speed Frame-Synchronizer is an absolutely necessarily key device of the Remote Sensing Satellite’s Ground-Receiving system. It is mainly used to format the high-speed data stream, so that computer can get the beginning address of every frame of the high-speed data stream, and then data stream would be send to computer for pretreatment through high-speed interface. The observing ground satellites of modem time have higher resolving power, so that they require ground station system with more performance accordingly. As the key device of ground station system, High-Speed Frame-Synchronizer needs to have higher performance also. High-Speed Frame-Synchronizer not only is required higher speed but also requires to be used for more kind of satellites. It is impossible to buy the High-Speed Frame-Synchronizer overseas because of high price, and more important, the way of data format and encrypt of military satellites is involved the secret of nation. We must research and produce the key device by ourselves. The achievement in the technique will help our country in constructing the system of new Remote Sensing Satellites and military satellite’s ground stations. The dissertation accomplishes the design, simulation and realization in software and hardware of High-Speed Frame-Synchronizer, which its highest speed is 150Mbps. The High-Speed Frame-Synchronizer can be used to work for many kind of satellites, and can be controlled<WP=5>by computer initializing. The High-Speed Frame-Synchronizer can be controlled by changing parameter as followings: IQ routes information, the length of frame head, the content of frame-synchronization codes, frame-synchronization error sufferance, frame protect sufferance, frame protect coefficient, the length of frame. To achieve design target, the author referred a great deal of correlated data, and accomplished hereinafter parts: compile programs of FPGA to realize main design, simulate system, protract high-speed PCB board, compile single chip machine’s programs for control, and debug experiment.The results of experiment indicates that the High-Speed Frame-Synchronizer’s design meet the request of high-speed and flexible control.更多还原