【作者】 孙尉恒；

【导师】 虞厥邦；

【作者基本信息】 电子科技大学 ， 电路与系统， 2003， 硕士

【摘要】 本论文基于电子科技大学和广州邮电通信设备有限公司合作的国家科技攻关计划课题——“专用短程通信（DSRC）设备”（编号：2002BA404A23A）的要求，进行了相关电路模块的理论研究，并针对其中本振信号源进行了实验，根据科研任务分工，本论文集中论述了频率合成技术中S波段小数频率合成器的设计及实现研究。首先，从锁相环的基本理论、原理出发，分析了锁相环中的三个基本部件：鉴相器、环路滤波器和压控振荡器，此后，针对线性化锁相环进行了分析，研究了在使用比例积分滤波器时，三阶锁相环的环路参数计算；在电路实现时选用了LMX2353，在此基础上，完成了2.2~2.5GHz范围内的小数频率合成器设计。并制作成功了高分辨率、快捷变的小数频率合成器的板级样品。最后，还进行了样品的性能测试，另外，还结合该实验产品，进行了电磁兼容分析。更多还原

【Abstract】 The thesis describes a prototype fractional frequency synthesizer which is supported by a project granted by the Ministry of Science and Technology of PR China. Firstly, based on the principle of PLL, this paper briefly describes three basic PLL components: Phase Detector (PD), Low Pass Filter (LPF), Voltage Controlled Oscillators (VCO) , analyzes the linearized PLL and summaries the transfer functions of third-order PLL with ideal intergrator filter respectively. Based on a microwave VCO, the single point frequency PLL frequency ranging from 2.2 to 2.5GHz is developed. Based on digital PLL, the S-band frequency synthesizer is manufactured. The characterstic of PLL , as well as the mathematical model of phase noise are also investigated. The paper presents the schematic of S-band frequency synthesizer and the main circuits modules upon which, by considering the Electromagenetic Comptiblity (EMC), fractional frequency synthesizer is fabricated by both PLL and DDS, the performance of the prototype product is carefully measured. Measuring results show that the product’s performance meets the pre-assigned specifications .更多还原