USB接口电路的设计与实现——发射端的设计

【作者】 辛宇；

【导师】 李平；

【作者基本信息】 电子科技大学 ， 微电子学与固体电子学， 2003， 硕士

【摘要】 USB是由Compaq，Digital，Equipment，IBM，Intel，Microsoft，Nec和Northern Telecom（北方电信公司）等七家公司共同提出的。USB的英文全称为Universal Serial Bus，中文含义是通用串行总线，它是一种快速的、双向的、同步传输的、廉价的并可以进行热拔插的串行接口，它是与当今计算机的发展趋势相适应的。之所以提出USB技术的主要原因就是想利用单一的总线技术，来满足多种应用领域的需要。在USB总线上，可以同时支持低速（1.5Mb/s）和全速（12Mb/s）以及高速（480Mb/s）的数据传输；而且可以支持异步(如键盘、游戏杆、鼠标)传输和同步传输（如声音，图象设备）等传输方式；它还可以同时支持多达127个外设。可见USB总线技术的提出使人们渴望利用单一的总线技术来实现多种外设同主机互连的梦想得以实现。 本文详细介绍了USB的特点、总线体系结构、数据传输模式、USB数据流模型、USB协议。让大家对USB系统、USB协议以及我们的工作开展有个大概的了解。在消化协议，深入理解协议的基础上提出设计USB接口电路的思想。对同步模式的识别、并行/串行转换、位填充/解除填充、CRC 校验/产生、PID 校验/产生、地址识别和握手评估/产生做了具体的分析。为将来的进一步硬件验证奠定了良好的基础，也增强了集成电路设计中心在通信协议方面的科研能力。采用自顶向下的设计方法，在充分了解系统的基础上，划分功能模块进行行为描述、RTL功能仿真、逻辑综合。在此基础上进一步做时序仿真和静态时序分析，产生byte文件，下载到FPGA进行实物验证。运用硬件描述语言--Verilog-hdl来完成代码设计，并使用Active-HDL和Synplify软件完成仿真和综合。同时本文对EDA软件（Active-HDL和Synplify）的使用也做了一定的介绍。更多还原

【Abstract】 Universal serial Bus is a new technology about interface between computer and device. USB technology has become one of the fastest developing technologies in recent years, and is widely used in the computer field. USB technology is single bus technology. USB bus supports not only low speed (1.5Mb/s), full speed（12Mb/s）and high speed（480Mb/s）data transmission but also asynchronous transmission (such as keyboard, play-pole, mouse), synchronous transmission (such as sound, image device) and other transmissions. USB technology implements connection between multi-devices and host. This paper mainly introduces feature of USB, bus system structure, data transmission method, data flow model of USB and USB protocol. An idea is brought forth to design USB interface circuit after comprehending the USB protocol. At the same time, this paper presents packet recognition, transaction sequencing, SOP, EOP, RESET, RESUME signal detection/generation, clock/data separation, NRZI Data encoding/decoding and bit-stuffing, CRC generation and checking (Token and Data), packet ID (PID) generation and checking/decoding, serial-parallel/ parallel-serial Conversion.In this design, codes are written in Verilog-hdl, simulated in Active-hdl and synthesized in Synplify, based on which, this paper also give timing simulation and static timing analysis results. In the final, byte file is given and downloaded into FPGA and tested. This paper has also introduced using of EDA software, such as Active-hdl, Synplify and etc.更多还原