空间谱估计算法的高速实现

【作者】 陈昊；

【导师】 魏平；

【作者基本信息】 电子科技大学 ， 通信与信息系统， 2003， 硕士

【摘要】 阵列测向在移动通信、电子对抗、参数估计、信号识别等等领域有着广泛的应用前景。空间谱估计技术是近40年来发展起来的一门空域信号处理技术，其主要研究方向为超分辨方向估计，可以应用在阵列测向中。空间谱估计技术经过多年的发展，已经产生了大量性能优异的测向算法可资利用。典型的有MUSIC、ESPRIT、子空间拟合、多维MUSIC等。在各种空间谱估计算法中，由R.O.Schmidt提出MUSIC算法【2,3,4】是一种基于子空间分解的算法，具有高精度（其估计方差接近Cramer－Rao方差下限）和高分辨率的特性，同时也运算量大的特点。而在阵列测向在许多应用场合中，如移动通信中的空分多址的应用；电子侦察和对抗在复杂、密集的实际信号环境中的应用等，都要求做出快速的反应，面临着高速实现、小型化、低成本的要求。因此研究MUSIC算法的实时实现对于促进更广泛的应用该算法有着十分重要的意义。本文主要研究了MUSIC算法在一个八阵元的均匀圆阵阵列测向系统上的高速实现的问题：1． 研究了一种针对八阵元均匀圆阵测向系统的预处理方法，该方法将MUSIC算法的计算从复数域转换到实数域上，从而有效的减少了计算量，该预处理方法对任意的偶数阵元的对称阵列都适用。2． 通过对MUSIC算法的各个步骤的分析，分别给出各步骤的并行化处理方案。3． 研究实现MUSIC算法的DSP＋FPGA、浮点运算与定点运算混合的硬件设计方案。4． 提出求解协方差矩阵的两种方案：串行处理方案和并行处理方案。在HP工作站上用SPW/HDS进行系统建模和行为级仿真；在微机上用VHDL语言进行RTL级描述、时序仿真和逻辑综合。并对两种方案的性能作出比较。5． 研究了用FPGA实现将协方差矩阵处理器得出的32位定点数转换为符合IEEE754标准的单精度浮点数格式的问题，得出了实用的方法，并给出了时序仿真和逻辑综合的结果。<WP=8>阵列测向在移动通信、电子对抗、信号识别等领域的应用对实时性要求越来越高，处理速度难以满足实际应用的需要成为了制约MUSIC算法应用的一个主要的瓶颈。本文在如何针对测向系统的特点来减少MUSIC算法计算量，以及采取多种措施来进行高速实现等方面，作了一些探索，得出了一些有益的结果更多还原

【Abstract】 Array processing technique has exhibited its brilliant future by its unique merits in recent years. Spatial spectrum estimation technique, a branch of array processing technique, has been developing in past 40 years. Lots of good methods and algorithm have been brought forward, and the MUSIC algorithm is one of them. The MUSIC algorithm, as a typical direction-of-arrival(DOA) estimation algorithm, is a subspace-based method with many excellent performances. It can find many applications, such as mobile communication, electronic reconnaissance, parameter estimation, signal discrimination, etc. Nevertheless, it needs huge quantity of computation, which baffles its further application. Therefore, it is very necessary to study its high-speed implement methods. This dissertation studies the high-speed way to apply MUSIC algorithm in an eight-sensor uniform circular array (UCA) system.The main contents of this dissertation are as below:1. A preprocess method are studied. Using this method, MUSIC algorithm’s computational complexity can be reduced greatly. 2. Researches the steps of MUSIC algorithms, and then introduced the parallel process methods for each steps.3. Studies the hardware design plan to implement MUSIC algorithm, which combines DSP implementation and FPGA implementation as well as fixed-point implementation and float-point implementation.4. Introduces two plans, which are serial process plan and parallel process plan, to implement correlation matrix computation. Both of plans’ system model and behavior simulation are completed by using Cadence company’s SPW/HDS development software, RTL simulation and logic synthesis are accomplished by using Synplify and Quartus in PC.5. Studies the methods of transfer data from fixed-point format to IEEE754 single precision floating-point format, and implement it in FPGA更多还原