【作者】 陈林；

【导师】 黄建文；

【作者基本信息】 江苏大学 ， 计算机应用技术， 2003， 硕士

【摘要】 集成电路制造技术的飞速发展，现在已经可以把一个完整的电子系统集成到一个芯片上，即所谓的系统级芯片(SoC)。系统级芯片的设计需要新的设计方法和建模工具。SystemC是OSCI(Open SystemC Initiative)组织制定和维护的一种开放源码的C++建模平台，它由一个定义良好的C++类库及仿真内核组成，支持对系统进行寄存器传输级，行为级和系统级的描述。SystemC的优点包括对软硬件联合设计的支持，更高效和方便的进行IP交换，以及在不同的抽象模型间复用测试基准的能力。 本文的研究内容首先是提出了一种基于SystemC的自顶向下的设计流程。这一设计流程基于系统的四层抽象模型：功能模型，事务模型，通信模型和实现模型。并以一个CSMA/CD MAC层协议的实现实例验证了这一设计流程，评估了SystemC在SoC设计中的优缺点。本文最后探讨了如何实现SystemC—VHDL的自动转换。采用Lex和Yacc作为辅助工具，实现了一个可以将部分SystemC代码转到VHDL的编译系统原型。更多还原

【Abstract】 Due to the development of 1C technology,now a complex system can be integrated in a chip called system on chip(SoC).The design of SoC needs new design methodologys and modeling tools.SystemC is an open C++ modeling platform promoted by the Open SystemC Initiative ,which consists of a well defined set of C++ classes and a simulation kernel,supporting design abstractions at the register-transfer, behavioral,and system levels.The advantages of SystemC include the ability for hardware-software co-design,the ability to exchange IP easily and efficiently,and the ability to reuse test benches across different levels of modeling abstraction.Firstly,a Top-Down design methodology based on SystemC is presented.The methodology is based on four system abstract models:Function Model,Transcation Model,Communication Model and Implementation Model.A CSMA/CD MAC protocol concrete example is presented to verify it,and Its advantages and disadvantages are also evaluated.Finally,the method for translating a SystemC source into an equivalent VHDL program is discussed.With the aided tools Lex and Yacc,a prototype of SystemC-VHDL translation system is implemented.更多还原