基于386EX CPU的实时EDAC设计

【作者】 周盛雨；

【导师】 陈小敏；

【作者基本信息】 中国科学院研究生院（空间科学与应用研究中心） ， 计算机应用技术， 2003， 硕士

【摘要】 由于辐射导致的单粒子翻转效应SEU（Single Event Upset），使得航天计算机上的静态存储器SRAM中的数据可能出现小概率错误，这种错误若不及时进行纠正将会影响计算机系统的运行和关键数据。本课题实现了基于386EX CPU航天计算机的实时EDAC（Error Detection and Correction）电路的设计，即采用纠错编码设计来完成对SRAM中的数据进行纠错的功能。本课题的研究工作建立在第一轮386EX CPU航天计算机最小系统设计成功的基础之上。本论文阐述了［12，8］汉明码纠错设计过程，采用VHDL语言实现纠错编码器（EDAC），本设计能够适应CPU时钟信号CLK2的不同频率，如66MHz、50MHz、40MHz、33MHz，并且能够通过软件的控制使FPGA的纠错编码功能关闭。此外还将第一轮设计中的基本逻辑器件如与、或、非门以及诸如244、255、译码器等小规模元器件都集成到FPGA内部来实现。本论文详细介绍了电路的设计过程并对时序仿真进行了分析。最终整个设计通过了硬件调试，正常工作。在第一轮设计中已经成功地完成了386EX CPU航天计算机的最小系统设计。本课题的成果连同原有的设计可以应用于我国载人航天、空间探测、卫星组网等任务中去，势必提高我国航天计算机的抗辐射、可靠性的能力，对推动我国空间科学技术的发展有很大的意义。更多还原

【Abstract】 Zhou Shengyu（Computer Application）Directed by Chen XiaominBecause of the radiation in space enviroment, the data in SRAM of the aerospace computer will nomally experience Single Event Upset (SEU) errors at a scale of small probability. Had not been corrected in time ,these errors would effect not only the performance of the computer system but also the transmission of the key data.. A method about how to design a real-time EDAC circuit based on aerospace computer which cantains 386EX CPUis is described in this paper.The main subject of this paper concentrates on the design of the EDAC (Error Dectection and Correction) circuit which can accomplish the function that correct the errors of the data in SRAM.Above all, [12:8] Harming error correction theory is mentioned in this paper.The EDAC circuit designed by VHDL can works normally at different frequency of the CPU clock such as 66MHz\50MHz\40MHz\33MHz. The EDAC function of the circuit can also be disabled by software tool.Meanwhile,some basic devices such as AND logic,OR logic,NOT logic and some small scale integrated circuits are also integrated in the FPGA.The designing process of the EDAC circuit is described in the paper. The time simulation is analysed, too. The designment of the circuit has access the hardware debug, and can woks normally.更多还原