嵌入式128Kb SRAM的研究与设计

【作者】 田虹；

【导师】 张志勇； 赵宁；

【作者基本信息】 西北大学 ， 电路与系统， 2002， 硕士

【摘要】 随着微电子技术水平的不断提高，SRAM呈现出更高集成度、更快速及更低功耗的发展趋势。近年来，集成SRAM的各种系统芯片已屡见不鲜，它们在改善系统性能、提高芯片可靠性、降低成本与功耗等方面都起到了积极的作用。本文主要针对应用于MCU的嵌入式128Kb静态存储器的设计进行了详细的阐述。文章结合存储单元静态噪声容限（SNM）及软误差率（SER）的分析，对静态六管单元进行了优化设计，在保证缩小芯片面积（存储单元的尺寸为：10.8×14.8um²）的同时提高了存储单元的工作稳定性(SNM_6T=713mv)。设计中采用了存储阵列划分、分级字线以及CMOS正反馈差分读出放大器等先进技术，读写速度可达到20ns。并且由于采用阵列划分技术，电路功耗减小为传统设计的1/8。芯片采用0.6um CMOS硅栅双阱双层多晶双层铝互连的制造工艺，芯片尺寸为：6.31×4.57mm²。SRAM的字长可在×8b、×16b、×32b间自行配置，方便了用户的使用。更多还原

【Abstract】 With the development of microelectronics the SRAM trends can be summarized as fast speed, large capacity and low power. In recent years, all kinds of chip embedded with SRAM is becoming more and more popular, which demonstrate excellent characteristics such as fast data store speed, high reliability and low dissipation power. In this paper a 128Kb full-CMOS SRAM is described which is embedded in a 32b MCU. Based on the analysis of the SNM and the SER, the device parameters of the 6T cell are optimized, which not only reduce cell size (the memory cell size is 10.8×14.8um2) but also make the SRAM more reliable (the SNM6T is 713mv). In order to improve the performance of the SRAM, array partition, divided word line structure and CMOS positive feedback sense amplifier are adopted. All of them not only improve the speed of the chip, but also reduce the power dissipation of the chip to the 1/8 compare with the traditional design. The access time of the SRAM is 20ns. The chip is fabricated by a double polysilicon, double metal and twin-well 0.6um CMOS process technology, and the chip size is 6.31×4.57 mm2. In addition, the chip can be configurated as a ×8b, ×16b or ×32b memory for the sake of convenience for the customer.更多还原