【作者】 陆涛；

【导师】 汪晓宁；

【作者基本信息】 西南交通大学 ， 交通信息工程及控制， 2003， 硕士

【摘要】 扩频通信系统与常规的通信系统相比，具有很强的抗人为干扰，抗窄带干扰，抗多径干扰的能力。并具有信息隐蔽、多址保密通信等特点。目前已从军事领域向民用领域发展。本论文主要讨论和实现了基于FPGA的扩频通信信号的基带处理。论文对扩频通信系统和FPGA设计方法进行了相关研究，尤其是对FPGA设计中的一些非常重要的严格同步问题进行了研究。最后用Xilinx公司的最新的FPGA开发平台ISE 4实现了一个基带扩频通信系统。 整个系统分为二部分，发送部分和接收部分。发送部分主要有串并处理、差分编码、PN码扩频、QPSK调制等模块。接收部分主要有数字下变频、数字匹配滤波器、积分清洗、功率检测、符号跟踪处理、差分解调、并串处理、自动频率跟踪处理等模块。 本论文工作的重点是在ISE 4开发平台上具体实现这个扩频系统，并对系统中的每个模块和整个系统进行相应的功能仿真和时序时延仿真。 论文的第一章介绍了扩频系统的特点以及相关扩频芯片的国内外发展现状，并介绍了本论文的研究思路和内容。 第二章主要介绍了论文所涉及的一些理论背景。主要是扩频系统的相关解扩、基带解调、同步以及扩频系统中的调制与解调技术。同时还介绍了用来实现这些模块的硬件描述语言—VHDL和Xilinx公司的ISE 4开发平台。 第三章给出了扩频通信系统的总体设计和发射及接收子系统的各个功能模块的实现分析以及在ISE 4上的实现细节。并进行了功能仿真和时序时延仿真，给出了仿真结果。 第四章主要介绍了在ISE 4上实现本系统时遇到的问题和解决的办法。重点讲述了FPGA设计中的严格同步问题，以及本人在ISE 4中应用VHDL进行设计时一些经验总结。 第五章主要是对论文工作的一些总结和对今后工作的展望。 附录中是论文中所有的源代码和底层的SCH(Schematic sheet)详细设计图。更多还原

【Abstract】 The spread spectrum (SS) communication system has stronger ability of resisting jamming, narrow band, and multipath interference than that of the conservation communication systems. And it also has the characteristics of low probability of intercept and multiple access secure communication. Nowadays, the SS technology has expanded from the military field to the commercial field. This thesis primarily discussed the baseband processing of SS communication signal based field programmable gate array (FPGA) ASIC chip. The design technique of FPGA related to SS communication system has been discussed in this thesis. Especially, the strict synchronous which is important in FPGA design has been discussed. Finally, the SS baseband communication subsystem has been designed and implemented based on the FPGA development platform ISE 4 belonging to the U.S. Xilinx Company.The total system can be divided into two parts, i.e., transmitter and receiver unit. The transmitter unit mainly consisted of the dibit-to-serial conversion, differential encoder, PN code generator and QPSK modulator and so on. The receiver unit mainly consisted of the digital down converter, matched filter, integration and dump module, power detector, symbol tracking processor, differential demodulator, parallel-to-serial conversion module, output processor and AFC module.The emphases of this thesis are to implement the SS baseband communication system and to achieve behavior simulation and post-place&route simulation respectively on the platform of ISE 4.Chapter one introduces the characteristics of the SS communication system and the development related .to SS ASIC chip at present in the world. It also introduces the outline and the research idea of the thesis.Chapter two mainly introduces the background related to the theory. It contains the despread spectrum, baseband demodulation, synchronization and the technology of modulate and demodulate in the SS system. Meanwhile, it also introduces the design platform-ISE 4 of Xilinx Company and the VHDL-a sort of hardware design describe language.In the chapter three, the analysis and the implement detail for all modules based on ISE 4, both transmitter and receiver unit, have been given in this section. The results of behavior and post-place&route simulation of all modules also have been represented.The problems and their solutions in the course of implement the design have been described in the chapter four. Emphatically, the strict synchronization in the FPGA design has been discussed. And in this chapter, some experiences of using VHDL to design by the platform ISE 4 have been represented.The summaries of the thesis and the possible extensions and improvements based on the completed system have been represented in the Chapter five.Finally, all the VHDL program code and the diagram of schematic sheet design are shown in the appendix.更多还原