节点文献
高速数模转换器的设计
【作者】 詹桦;
【导师】 韩雁;
【作者基本信息】 浙江大学 , 微电子学与固体电子学, 2003, 硕士
【摘要】 本项目的目的是设计一个10bit高速数模转换器(DAC)的IC芯片。 随着计算机技术、信号处理技术、微电子技术的快速发展,先进的电子系统不断涌现。在许多电子系统的后端,应用了数模转换器。特别是在无线通信等领域,需要用到高速的数模转换器。在通信日益发达的今天,高速DAC的前景广阔。 在比较了数模转换器的众多结构之后,本设计决定采用分段式的电流型结构。其中,10bit DAC的高6位采用一进制编码,可以减小误差,加快速度;低4位采用二进制编码,可以减小面积。输入输出方式是并行输入,电流输出,这也符合高速的目标。 数模转换器的内部电路包括电流源矩阵、基准源等模拟电路模块,以及寄存器、译码器、锁存器等数字电路模块,属于数模混合电路。由于本设计对数字电路部分的要求比较严格,而且电路结构相对简单,所以采用和模拟电路设计一致的设计方法,即:使用原理图输入设计,全定制编辑版图,对版图进行DRC,LVS以及后模拟验证。使用的是Cadence中的一系列CAD工具。 本设计是采用无锡华晶上华半导体有限公司的0.6μm双阱、双多晶硅、双金属的5伏标准CMOS工艺实现的。芯片共21个管脚,面积为2mm×1mm=2mm~2。 测试得到的微分线性误差和积分线性误差分别为-1~+1LSB、-1~+1.5LSB。
【Abstract】 The purpose of this project is to realize a design of a 10-bit high-speed digital-to-analog converter (DAC).With the fast development of computer technology, digital processing technology and microelectronic technology, advantaged electronic systems are presented continually. DACs are applied to the back-end of some of them. Especially, high-speed DACs are needed in the area of wireless communication. During the time of fast development of communication, the high-speed DAC is very promising.After comparing with many structures of DAC, the segmented architecture of current scaling DAC is decided. The 6 MSBs are unity-weighted to reduce error and increase the speed of DAC. And the 4 LSBs are binary-weighted to reduce area of DAC. The mode of input is parallel-input and output current-output.The DAC consists of analog circuit blocks (current matrix and reference) and digital circuit blocks (register, decoder and latch). So it’s a mixed signal circuit. But, because the digital part’s design demand is strict and its structure is simple, we use the same method as analog part to design it. It’s to draw schematic and customize layout manually, edit the DRC\ LVS files to verify the layout and finish the post-simulation. A series of EDA tools of Cadence are used.The chip is fabricated on the 0.6-um CMOS process (twin well, double poly and double metal) of CSMC. The chip area is 2mm X lmm=2mm2.The INL and DNL of the DAC chip are 1-+1LSB, -1-+1.5LSB, respectively.
- 【网络出版投稿人】 浙江大学 【网络出版年期】2003年 02期
- 【分类号】TN792
- 【被引频次】4
- 【下载频次】601