【作者】 张力；

【导师】 苏龙滨；

【作者基本信息】 哈尔滨工程大学 ， 信号与信息处理， 2002， 硕士

【摘要】 由于海洋声信道结构的复杂性，声呐信号处理始终是信号处理领域中最复杂的分支。当前，声呐技术发展的最重要的一个特征是大量采用数字信号处理(DSP)技术。但是，现代计算机的处理速度仍然与实际应用的需求存在较大的差距。由于并行处理蕴含着提高处理速度和解决大规模问题的巨大潜力，展现出由多处理机组成更大的计算系统的广阔前景，并行信号处理已成为现代数字信号处理的一个重要特点。因而其信号处理机的出路在于体系结构的并行化。 本论文采用当前国际上较流行的DSP器件ADSP21060(SHARC)，设计和实现了一个基于PCI总线的四片ADSP21060并行信号处理板。由于采用了先进的DSP处理芯片和结构、流行的高速总线PCI总线、大规模FPGA及VHDL硬件描述语言进行接口逻辑设计，使得本设计的整个系统具有相当的水平。本设计开发的并行处理机具有良好的可扩展性，可扩展成具有复杂拓扑结构的信号处理机以适应不同规模的并行算法的要求。 本论文主要研究内容包括：1．四片ADSP21060并行信号处理机的研制。其中包括板子的总体设计，原理图设计、电路板设计，电路板焊装与调试。2．采用FPGA器件，并利用VHDL语言完成逻辑设计PCI接口芯片S5933的ADD-ON总线与SHARC的HOST INTERFACE的接口逻辑。3．PCI总线设备驱动程序的编写。4．SHARC的HOST INTERFACE的调试。包括数据的读写，SHARC的BootLoad。更多还原

【Abstract】 Sonar signal processing remains the most complicated branch in the field ofsignal due to such reason as the comPlexity of underwater acoustic channels. Themost important characteristic of the development of sonar technology is using thetechnology of digita1 signal proccssing widely. But the processing rate doesn’tmeet the need of practical applications. Because the parallcl processing remainsthe latent capacity of raising the processing rate and solving the mass problem,parallel signal processing became an important characteristic of the modern digitalsignal processing. So the egress of digital processing systern lies in the parallelarchitecture.In this paPer, a signal processing system based on PCl bus is designed andcompleted, Which is made up of fOur chips of ADSP21060 (SHARC) which themost advanced parallel DSP device. Becausc of using the advanced DSP, popu1arhigh speed PCI bus and laxge scale FPGA, using VHDL hardware descriptivelanguage to design the interface logic, the level of designed hardware is to acertain degree. This parallel processing system can be easily expanded to morecomplicated architecture to adaPt to the various parallel algorithIns.In this paPer, the main works are as fOl1owsf 1.A para1lel signal processingsystem with fOur ADSP2l060 processors has been developed. 2. By using FPGAand the VHDL hardwa-re descriptive language, the interface logic between theADD-ON bus of S5933 and the Host interface of SIlARC is designed andrealized.3. The driver of the PCI bus device is compiled. 4. The data reading,writing and BootLoad through the SHARC’s Host interface have been debugged.更多还原