数字复接器的FPGA设计与实现

【作者】 范丽珍；

【导师】 周正欧；

【作者基本信息】 电子科技大学 ， 信号与信息处理， 2002， 硕士

【摘要】 本课题主要是用FPGA实现一个数字复接器。其主要功能是在复接端将四个支路的2.048Mbps数据通过正码速调整技术，将其合路成一路8.448Mbps的高速数据流，在分接端又将此高速数据流恢复成原来的四路2.048Mbps的数据。此支路低速数据流与高速数据流既可以是没有编码的一般的非归零码流，也可以是编成了适合于在线路上传输的HDB3线路码。本课题中的时钟提取部分和平滑时钟部分都是用的锁相环来实现的。本文首先分析了线路码的一般问题；其次分析了正码速调整的基本原理及所涉及的一般问题，并说明了用FPGA进行电路设计的一般方法；最后分析了本系统所产生的抖动，如抖动的产生，分类以及如何减小抖动等，并对本课题所产生的两类抖动即正码速调整引入的侯时抖动和平滑锁相环引入的抖动进行了分析，并用Matlab仿真工具对锁相环的抖动与其环路带宽之间的关系进行了仿真与计算。 本人的工作主要包括： 1．利用FPGA完成了复接、分接系统的设计和调试。 2．利用FPGA完成了HDB3线路码的设计与调试。 3．利用锁相环完成了码速恢复。 4．对本复接分接系统所产生的抖动进行了理论分析和仿真。 5．对FPGA进行了误码率测试，误码性能优于10^-9。更多还原

【Abstract】 The subject is mainly accomplish a digital multiplexer by FPGA. The function can be accomplished that multiplexes four branches of 2.048Mb/s into one data flow of 8.448Mb/s and then demultiplexes the data flow into four branches, positive justification used during the course of multiplex. The code of the four branches can be the NRZ or HDB3 who is appropriate to be transmitted for a long distance. The clock recovery circuit and clock smooth circuit are accomplished with phase-locked loop (PLL) in this subject. In the article, at first, common problems of line coding are analysed; the second, the elementary theory of positive justification is analysed, and the general method about how to design the digital circuit with FPGA is narrated; At last, the author had analysed the jitter in this subject, such as the jitter generation classification and how to minimize jitter, analysed the waiting jitter introduced by positive justification and phase jitter introduced by the phase-locked loop circuit, simulated and calculated the relationship between the jitter of phase-locked loop and its bandwidth with the Matlab.The following tasks are performed by the author:1. The design and debug of the multiplex system and demultiplex system are accomplished by FPGA.2. The design and debug of line coding HDB3 are accomplished by FPGA.3. The gappy clock is recovered by the PLL.4. Jitter generated in the multiplexer and PLL are analysed and simulated.5. The error bit rate of the multiplexes is tested with the error and jitter test set, and the error bit rate is up to 10"9.更多还原