特种芯片集成中的可测性设计

【作者】 舒昶；

【导师】 吕述望；

【作者基本信息】 中国科学院研究生院（电子学研究所） ， 通信与信息系统， 2002， 硕士

【摘要】 大规模集成和超大规模集成电路迅速发展，使芯片的集成度越来越高，而供外部测试的引脚却很少，测试问题日趋困难，甚至使芯片测试比芯片本身的设计和生产要付出更高的代价。为了减少测试的困难，人们普遍接受的途径是在设计过程中注意到电路的可测性，即所谓可测性设计。在系统级开发的过程中需要优先解决可测性问题，特别是设计系统级芯片会用到很多数字线路和IP内核。长期以来在可测性设计阶段，故障覆盖率一直是测试设计关心的重要课题，如今在一个芯片中包含了如此多种类型的线路，更为解决测试覆盖率问题增加了难度。一个好的可测性设计不仅要具有较高的故障覆盖率，而且测试模块所占芯片面积要做到尽量的小，以便少占用资源。本文从可测性设计的基础理论出发（包括门级电路的可测性测度、功能级上的可测性和可控性、可测性设计的流程和方法等），介绍了现代常用的可测性技术，比如：扫描技术、内嵌自测试技术等，特别是边缘扫描技术已经广泛地应用到VLSI的可测性设计之中，它通过特定的控制器，从相应的测试输入端口将测试向量扫描至芯核所对应的管脚，再将结果从相应的测试输出端口扫出。而内嵌自测试技术对于解决SOC生产测试的问题非常有效，它将一个激励电路和响应电路中加到被测电路中，从而使测试人员不必再考虑测试向量的问题，因为它是自动生成的。在此基础之上，本文讨论了SSX01的可测性设计，对各种可能的方案进行了比较，最终提出了ROM和运算核等模块的测试解决方案。更多还原

【Abstract】 With the sharp development of LSI and VLSI, the integration of chip gets denser and denser. But the extra ports for testing is limited and test is more difficult than before. We even must spend more time and money on chip testing rather than chip design. In order to allay the difficulty of test, one should pay attention to the Design For Testing (i.e. DFT) during the period of system design. In the process of system developing, the engineer should first solve the problem of DFT, especially when lots of digital circuits or IP cores are used in System On Chip. The ratio of fault covering has always been the focus of testing designer in DFT for a long time. Now a single chip contains all kinds of circuits, so to solve the problem of the ratio of fault covering is even harder than before. A sound DFT not only has a high ratio of fault covering but also occupies little area of a chip in order to lower the usage of sources. From the view point of the foundation of DFT (which includes the testable measure of gate-level circuits, the testable and controllable measure of functional-level, the flow and methodology of DFT and so on), the author introduce some common testing technology such as scan and BIST in modern times. Especially the Boundary Scan Technology has been widely adopted in the DFT of VLSI. With the special controller, the testing vector could be scanned to the corresponding ports of inner cores from the testing input ports, and the response could also be shifted to the testing output ports. BIST is an efficient solution for the testing of SOC. It is built up with prompting and responding circuits and these two parts are added to the circuit being tested so that the engineer need not consider the testing vector, for it’s generated automatically. Furthermore, the author also discussed the DFT of SSX01 (which is a kind of cipher chip) and compared all kinds of testing solutions, finally presented the DFT of the module of ROM and operation core更多还原