【作者】 崔月霞；

【导师】 赵振纲；

【作者基本信息】 北京邮电大学 ， 信号与信息处理， 2013， 硕士

【摘要】 随着计算机应用对带宽需求的日益增长,PCI Express总线协议作为PCI-SIG规范并标准化的第三代高性能的IO总线技术,拥有点到点的串行数据高速传输等诸多优势,成为未来总线技术的发展趋势。高速数据传输系统是指上位机服务器和下位机硬件平台通过PCI Express桥芯片实现高速通信的DNS防火墙设备。本课题首先对PCI Express总线协议作了基本论述,然后对DNS防火墙系统从硬件、软件和应用程序三方面作了概述。最后重点对PCI Express桥芯片的设计作了详细阐述。课题采用Altera芯片厂商的Cyclon IV GX系列的FPGA实现,该FPGA内嵌了PCIe的IP硬核,该硬核实现了PCI Express总线协议的事务层、数据链路层和物理层的功能,所以课题只需要对PCI Express协议的应用层进行逻辑设计。应用层逻辑设计实现了单包读写(PIO)通路和DMA读写通路两种数据传输方式。课题首先对高速数据传输系统进行需求分析,然后给出了基于FPGA的PCI Express桥芯片的设计方案,包括逻辑设计框图、接口说明及总线时序等。在此基础上,采用Verilog HDL硬件描述语言完成了应用层的RTL代码设计,实现了PIO通路和DMA通路功能。最后对高速数据传输系统进行系统级仿真验证,测试结果表明：PCIExpress桥芯片采用X1通道,DMA通路的读数据传输速率达到168MB/S,写数据传输速率达到172MB/S,满足上位机服务器和下位机硬件平台进行高速通信的速率要求。此外,还根据需求扩展到X4通道获得更高的传输速率。目前,DNS防火墙设备成功在线上部署,并得到广泛应用。更多还原

【Abstract】 With the growing demand of bandwidth for computer application, PCI Express bus specification, as the Third Gneration Input/Output standard, own many advantages such as point to point transimission and serial data stream which makes it become the trend in bus technology field.The high speed data transmission system refers to the DNS firewall device which implements the communication between the upper server host and lower hardware board through the PCI Express bridge chip. The first part describes the basic principle of PCI Express bus protocol. The second part gives the overview on the DNS device which consists of the hardware, software and web application. The last part presents the design and implementation of the PCI Express bridge chip based on FPGA.The FPGA of Altera Cyclon IV GX family chip, embed with PCIe IP core. The hard IP core implements the functions of transaction layer, data link layer and physical layer. So the subject needs to implement the logic design on PCIe application layer. The application layer is designed to implement programming input/output transmission and DMA transmission.The subject makes a demand analysis on high speed data transmission system, then gives design scheme of PCI Express bridge chip, including logic design block diagram, interface description and bus timing. On the basis of scheme, the RTL coding is used in Verilog HDL language to implement PIO transmission and DMA transmission. In the end, the simulaiton of high speed data transmission system shows that DMA read data rate is168MB/s, DMA write data rate is172MB/s. So the design meets the requirements of high speed rate between upper server host and lower hardware board. In addition, we can expand the design by using X4channel to get higher speed rate. Now, the DNS firewall is deployed and used successfully.更多还原