【作者】 陶永燕；

【导师】 姜军；

【作者基本信息】 北京邮电大学 ， 通信与信息系统， 2013， 硕士

【摘要】 本文课题来源于北京邮电大学和某公司联合承接的LTE终端测试设备开发项目,作者主要负责基带板核心处理器TI C66系列DSP底层接口驱动的设计与实现,具体包括DSP启动方案和高速接口通信两大部分。其中,在启动方案部分,主要设计实现DSP的SPI启动、PCIe启动及多核启动功能；在高速接口部分,重点实现三种高速串行接口AIF2、HyperLink和PCIe的通信功能。本文在绪论中概述LTE通信系统的架构及新特性,给出论文的课题背景和研究内容。第二章概述LTE终端测试设备的架构,并重点介绍基带板卡的设计和C66x DSP,给出论文的硬件平台基础。第三章主要介绍启动方案设计部分,根据板卡启动需求和C66xDSP的启动原理,编程实现SPI启动、PCIe启动以及多核启动功能。接下来是高速接口实现部分,共涵盖三章内容。其中,第四章首先概述基带板的三种高速串行接口,接着重点研究AIF2接口及其传输协议、同步机制,并编程实现DSP和FPGA之间的AIF2通信功能。第五章着重研究HyperLink接口及其传输协议,并编程实现两个DSP之间的HyperLink通信功能。第六章着重研究PCIe接口及其传输协议,并编程实现PC和DSP之间的PCIe通信功能。最后一章对论文做出简要总结,并提出展望。基带板是LTE终端测试设备的重要组成部分,DSP是基带板上的核心处理器。本论文将研究并实现C66x DSP的多种启动方案和高速接口通信,从而使DSP能够成功应用于基带板,对LTE终端测试设备的开发具有重要意义。更多还原

【Abstract】 This thesis comes from an LTE terminal test set development project, which is undertaken by Beijing University of Posts and Telecommunications and a company. The author is mainly responsible for designing and implementing the underlying interface drivers for TI’s C66series DSPs on the baseband board, including boot methods and high-speed interface communications. In the first part, SPI boot, PCIe boot and multicore boot function are implemented, while in the second part,3kinds of serial high-speed interfaces AIF2, HyperLink and PCIe are researched and designed for normal communications.At the beginning of this thesis, the architecture and new characteristics of LTE communication system are briefly reviewed, and then the background and main contents of the thesis are presented.The second chapter outlines the architecture of LTE test set, and then highlights the baseband board design and C66x DSP, showing the hardware platform of the thesis.The third chapter mainly describes the boot methods design part, according to the boot demands of the board and the boot principles of C66x DSP, the thesis designs and finishs DSP’s SPI boot, PCIe boot and multicore boot function.The next is the high-speed interface design part, covering a total of three chapters. The forth chapter first outlines the3high-speed serial interfaces on the baseband board, and then focuses on studying AIF2interface and its transport protocol, synchronization mechniasm, and finally finishes the AIF2communication between DSP and FPGA. The fifth chapter focuses on the research of HyperLink interface and its transport protocol, and then implements the HyperLink communication between the two DSPs. The sixth chapter focuses on the resarch of PCIe interface and its transport protocol, and then completes the PCIe communication between PC and the two DSPs on the board.The last chapter makes a brief summarization of the whole thesis.As an important part of the LTE terminal test set, the baseband board’s core processor is DSP. This thesis designs and implements different boot methods and high-speed interface communications for the C66x DSPs, so that they can be successfully used on the baseband board, which has great significance on the development of the LTE terminal test set.更多还原