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恒跨导CMOS轨对轨运算放大器设计

Design of Constant Transconductance CMOS Rail-to-rail Operational Amplifier

【作者】 马玉杰

【导师】 杨建红;

【作者基本信息】 兰州大学 , 微电子学与固体电子学, 2013, 硕士

【摘要】 随着便携式电子产品的飞速发展,集成电路电源电压不断降低,迫使运算放大器(以下简称运放)输入输出信号摆幅不断减小,进而严重影响运放的工作性能,甚至不能正常工作。为了提高运放的信噪比,通常需要输入输出信号范围能够达到整个电源电压,即轨对轨(Rail-to-Rail)。本论文在深入了解国内外轨对轨运放研究动态的基础上,基于标准CMOS工艺,研究如何实现低电压运放的输入输出达到全摆幅,以及如何实现输入级跨导恒定和输出级的高电源利用率。研究了各种电路的组成结构和工作原理,主要研究轨对轨输入/输出和恒跨导的实现方法。在吸收已有的相关技术成果基础上,自主提出设计方案,完成设计与验证。本论文设计的是一种3.3V低压轨对轨运算放大器。该运算放大器采用三倍电流镜法控制互补差分对作为输入级,不但满足了轨对轨共模输入电压范围的要求,而且具有良好的恒跨导特性。运放采用浮动电流源控制的前馈式AB类输出级,在精确控制输出晶体管电流的同时,满足了轨对轨输出电压动态范围的要求。运放采用折叠式共源共栅电路作为中间增益级,除实现电流求和及稳定静态输出电流的功能外,还可提高环路增益。对于所做的设计,基于CMOS工艺规范,采用Cadence Spectre工具进行了仿真。仿真结果表明:在电源电压3.3V、负载电阻5kΩ、负载电容10pF的情况下,运放直流开环增益为120dB,单位增益带宽为6.55MHz,相位裕度为66.4。,功耗为0.36mW,在整个共模范围内输入级跨导变化率仅为2.45%。整个电路结构简单紧凑,适合于低电压低功耗应用。

【Abstract】 Integrated circuits continue to lower the supply voltage, with the rapid development of portable electronic devices, which will force the input and output signal swing of operational amplifier (here in after referred to as the op-amp) greatly reduced, and which can seriously affect the performance of op-amp, even not to work. In order to improve the signal-to-noise ratio of the op-amp, the input and output signal range of op-amp usually requires to reach the entire supply voltage, Rail-to-Rail.Based on the understanding of the domestic and international research on Rail-to-Rail operational amplifiers, the paper studies how to accomplish the input signal scope and the output signal scope to achieve the entire amplitude of the low voltage op-amp and how to accomplish input stage with stable transconductance and output stage with high voltage efficiency, in the view of standard CMOS technology. It also studies the structure and the principles of electric circuits, including how achieves Rail-to-Rail input/output stage and the constant transconductance. On the basis of the related technical achievement, improved design proposal has been put forward and confirmed feasible implementation.A Rail-to-Rail operational amplifier is designed at3.3V single power supply. The input stage which satisfies the demand of Rail-to-Rail common mode input range with significant constant transconductance characteristics is a complementary differential pair controlled by three-times current mirror; the op-amp employs a feed-forward biased class-AB output stage controlled by the floating current source, meeting the requirements of the Rail-to-Rail output voltage dynamic range with precise control of the output transistor current. The folded-cascode structure is used as intermediate amplifier stage, which can realize the function of summing circuit and the steady static output current and increase the loop gain.Based on0.18um CMOS technology, Cadence Spectra tool is used for the simulation. With the supply voltage3.3V, the load resistance5KΩ, and the load capacitance10pF, the simulation results indicate that the operational amplifier has achieved open loop DC gain of120dB, unit gain bandwidth of6.55MHz, phase margin of66.4degree, power dissipation of0.36mW, and the transconductance variation over the common-mode input range of only about2.45%. For its simple and compact structure, this operational amplifier cell is suitable for low voltage and low power consumption application.

  • 【网络出版投稿人】 兰州大学
  • 【网络出版年期】2013年 11期
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