智能锁相放大器的设计

【作者】 任云杰；

【导师】 沈永良；

【作者基本信息】 黑龙江大学 ， 检测技术与自动化装置， 2012， 硕士

【摘要】 锁相放大器，特别是数字型的正交矢量锁相放大器，是微弱信号检测领域里的主要仪器，它具有测量精度高，稳定性好，信噪比高等突出优点，被广泛应用在物理、化学、生物、医学以及多种工程领域中。为了满足实时性高、运算速度快、精度高等要求，本文选用了ARM和FPGA组成的嵌入式平台进行智能锁相放大器的系统设计。本文围绕数字型正交矢量锁相放大器设计，首先，介绍了它的工作原理和基本结构，分析了影响其性能的主要参数采样频率、低通滤波器的截止频率、阶数等，提出了基于ARM和FPGA嵌入式平台的智能锁相放大器的解决方案。其次，根据数字型的正交矢量型锁相放大器的结构，设计了系统的硬件，选择了AD8331作为信号通道的前置放大器和可变增益放大器，可提供20M的带宽，74.5dB的增益；选择了AD9430作为模数转换器，可提供120M的采样速率，375μV的分辨率；选择了AD9518-1为模数转换器提供采样时钟，设置采样时钟在12.5M到120M可调；利用FPGA(EP3C10)设计了频率分辨率为0.028Hz，最高频率为20MHz的参考信号生成器、相敏检波器、IIR低通滤波器、相位和幅值运算模块等；以及各个部分之间接口的设计，主要是ARM和FPGA之间的接口，ARM与采样时钟生成器之间的接口等。再次，根据智能锁相放大器的控制功能，设计了系统的软件，包括在ARM平台上新添加的硬件设备FPGA和时钟生成器驱动的设计，以及基于Linux操作系统上的QT应用程序的设计等。最后，结合先前的设计，分析了实验的结果，给出了所设计的智能锁相放大器的指标。更多还原

【Abstract】 Lock-in amplifier, especially digital orthogonal vector lock-in amplifier, is themain instrument in the field of weak signal detection, which has high accuracy, goodstability, high SNR prominent advantages, and has been widely used in physics,chemistry, biology, medicine, and a variety of engineering field. In order to meet thehigh real-time, a fast calculation speed and high precision requirements, this paperselects the ARM and FPGA embedded platform to design intelligent lock-in amplifiersystem.This paper focuses on the design of digital orthogonal vector phase-lockedamplifier design. First of all, this paper introduces its principle and basic structure, andanalyzes the main parameters such as sample frequency, cut-off frequency and order ofthe low pass filter, and so on, impacting its performance, and put forward based onARM and FPGA embedded platform of intelligent lock-in amplifier solutions. Second,according to the structure of digital orthogonal vector phase-locked amplifier, design thesystem hardware, mainly including choosing AD8331as the preamplifier and variablegain amplifier in asignal channel, which can provide the bandwidth of the20M,74.5dB gain; choosing the AD9430as ADC, which can provide120M sampling rate,375μV resolution; choosing the AD9518-1as adc sampling clock, which can set thesampling clock in12.5M to120M adjustable; using FPGA (EP3C10) design thefrequency resolution for the0.028Hz, the highest frequency of20MHz reference signalgenerator, phase sensitive detectors, IIR low-pass filter, phase and amplitude operationmodule, etc. Again, according to control functions of the intelligence of phase-lockedamplifier, design the system software including new add hardware, FPGA and clockgenerator drivers design on the ARM platform, and QT application design based on theLinux operating system etc. Finally, combined with the previous design, gives indexesanalysis according the results of the simulations and experiments.更多还原