【作者】 白杰；

【导师】 杨建红；

【作者基本信息】 兰州大学 ， 微电子学与固体电子学， 2012， 硕士

【摘要】 随着非挥发存储器进入20nm工艺节点,传统的基于多晶硅浮栅结构的存储器在结构性能上遇到很多限制,其中最重要的问题是由于器件可靠性导致的尺寸无法按照等比例缩小的原则继续推进。为此,研究者们提出了多种新的挥发存储器结构,具有擦写速度快、可靠性高、制作工艺简单、成本低、与传统CMOS工艺完全兼容等优点的电荷俘获存储器以其分立存储的特性,成为多晶硅浮栅结构的最有潜力的替代方案之一。然而,目前电荷俘获存储器的研究中仍有许多问题需要解决。本论文首先回顾了非挥发性浮栅存储器的工作原理以及其在可微缩化发展上所面临的挑战,提出电荷俘获存储器的产生背景、发展历程以及工作原理。通过对电荷俘获存储器各功能层研究进展的分析和总结,指出了目前研究中存在的问题以及可能的解决方案。论文对基于氮化硅存储层的电荷俘获型存储器中涉及到的物理机理及物理模型,包括衬底电子进入存储层的各种隧穿方式、存储层陷阱能级在实空间和能量空间上的分布、电荷在存储层材料(氮化硅)中的迁移率、电荷的俘获及释放过程等做了详细分析,并在模拟过程中做了针对性的选择或处理。器件在编程和擦除操作时隧穿氧化层中的电场较大,通过陷阱辅助隧穿进入存储层的几率较小,在模拟中可不需考虑。在存储层陷阱能级的分布上,实验报道的能级分布有高斯分布、指数分布等等,但其分布的能级范围都很窄,所以可将其看作是单一的能级分布。对于被俘获的电荷从陷阱能级中的释放过程(机理),结合两性陷阱模型与Poole-Frenkel效应,本文对此做了详细的分析与讨论,给出了一种较为合理的模型解释,并将其用于数值模拟。将上述涉及到的模型方程加入电荷在存储层中输运的漂移-扩散方程和电流连续性方程中,形成耦合的方程组,通过对存储层网格化的方法将其离散,并利用牛顿迭代的方法对方程组进行求解,模拟了存储器的编程、擦除特性以及数据保持特性。本论文也研究了功能层厚度、陷阱参数等对器件特性的影响。SONOS结构存储器的编程速度随着隧穿层的厚度的增加而下降,但在隧穿层与阻挡层总的厚度不变的情况下,改变隧穿层的厚度对器件的编程速度没有影响；而对于TANOS结构,增大阻挡层的厚度并没有对器件的数据保持特性带来很大的改善,这验证了隧穿氧化层是数据保持状态下电荷泄漏的主要途径。对于文献中给出的不同的陷阱能级深度,我们对其编程和擦除特性进行了模拟,结果发现编程速度几乎没有变化,而擦除速度随着陷阱能级深度的减小而增加,主要的原因应该是更浅的陷阱能级深度导致了擦除时存储层陷阱中电荷释放到导带的数量增加。更多还原

【Abstract】 For the20nm-node non-volatile memory (NVM) technology. Flash memories with polysilicon floating gate have encountered serious technical challenges confront severe performance limitation:the contradiction between high speed, low power operation and longtime retention. In order to solve this problem, a lot of new non-volatile memory devices have been invented. Among those memories, owing to the discrete storage, the advantages of fast programming/erasing speed, high reliability, process simplicity, low cost, and compatible with conventional CMOS (Complementary Metal Oxide Semiconductor) process make charge trapping memory as one of most attractive candidates to replaces floating gate cell.In this thesis, firstly, a retrospect of the operating principle of non-volatile floating gate semiconductor memories and various challenges to its further scalability is conducted, and then the background and evolution of charge trapping memory is presented. After that, existing problems in charge trapping memory are pointed out and new solutions proposed through analyzing and summarizing the progress.The model and mechanisms of silicon nitride based charge trapping memory is analyzed in detail, including the model of charge tunneling into trapping layer, energetic and spatial distribution of traps, the mobility model and trapping-detrapping process. The trap-assisted tunneling can be ignored because of the high fields in programming and erasing. The energetic distribution range is very limited, although exponential and Gaussian distribution has been proposed, so it can be set to single-energy level. The detrapping process of charge from trapping center is discussed in detail. An electron will not experience the Poole-Frenkel effect if the amphoteric trap model and the hypothesis of all the traps being neutral in fresh device are used simultaneously; a reasonable model is given to resolve the contradiction and applied to the simulation.Above-mentioned models are incorporated in drift-diffusion equation and current continuity equation of charge transport in the storage layer, the coupled equations is discretized using the Newton iterative method in trapping layer, and to solve the equations to simulate the memory programming, erasing and data retention characteristics.Simulations are done with different layers thickness, traps parameters. Increase in tunneling layer result in higher tunneling current and faster programming, but if the overall thickness of tunneling and blocking layer, the programming speed remains constant. Increase in temperature will result in higher tunneling current and degraded retention. Simulation shows that shallow trap level result faster erasing but no influence the programming, this may be caused by higher charge loss for shallow trap level.更多还原