【作者】 高帅娜；

【导师】 毕春娜；

【作者基本信息】 大连海事大学 ， 电子科学与技术， 2012， 硕士

【摘要】 随着信息化和数字化社会的发展,人们对信息安全和保密的重要性的认识不断提高,如何有效保护计算机的信息安全已经成为IT界研究的热点。针对这种隐患的存在,本文以FPGA为平台将USB接口、AES加密技术和EDA技术相结合,采用SOPC软硬协同的方式设计了PC机外接数据加密设备。在不占用计算机硬件资源的情况下,实现了PC机上的数据的加解密,保证了PC机中数据的安全性。并且密钥固化在FPGA芯片中,不用担心忘记密钥而带来的不便。本设计既具有FPGA本身的高速性,安全性以及软件方面的易维护性和灵活性,又带有USB的热插拔,即插即用等功能,使用方便,而且性价比高。系统开发的硬件平台是FPGA,操作系统平台是Microsoft Windows XP,开发工具是QuartusII9.O、 SOPC Builder和NiosII IDE、 Microsoft Visual C++。系统结构包括软件和硬件两部分。PC主机负责上位机软件部分,完成用户应用程序界面的开发；FPGA开发负责硬件部分,完成AES算法模块和USB接口控制器的开发,其中AES算法单元采用硬件描述语言Verilog实现,由加解密模块、数据缓冲模块、控制模块和密钥扩展模块组成,实现数据的加解密；USB接口控制器采用SOPC软硬结合的方式实现,由SOPC硬件系统平台和NIOSII软核驱动程序两部分组成,实现开发板和PC机之间的通信以及对AES算法模块的控制。本文首先介绍了设计的背景、FPGA的开发流程、开发环境以及开发工具。接着详细介绍了系统整体设计和实现方案包括AES算法的实现,硬件系统的配置和软件系统的编程。最后介绍了系统上位机的设计和系统仿真与硬件调试。更多还原

【Abstract】 With the development of information technology and digital society, it is an increasing awareness of the importance of information security, and how to protect computer information security has become the research focus in the IT sector. In this article, USB interface, AES encryption technology and EDA technology are combined in an FPGA, designed of a PC external data encryption device, using the SOPC hardware and software in a concerted way. In the case of the occupation of computer hardware resources, this design can achieve data encryption and decryption on a PC, which guarantees the security of the data. And the key is fixed in the FPGA chip, so we do not have to worry about the inconvenience brought by forgeting the key. This design has both high-speed FPGA itself, security and easy maintenance and flexibility of software and hot-swappable, plug and play of USB, easy to use, cost-effective.System development hardware platform is FPGA;the operating system is Microsoft Windows XP; development tools are QuartusII9.0, SOPC Builder, Nios II IDE and Microsoft Visual C++.The design is divided into two parts of the software and hardware system. The PC needs to complete the development of user applications and the FPGA needs to complete the hardware development system. Hardware includes the unit of AES algorithm, the USB controller. AES, using hardware description language Verilog, contains the encryption and decryption module, the data buffer module, control module and the key expansion module. AES can achieve the data encryption and decryption between PC and FPGA; USB controller, using SOPC hardware and software combination and containing SOPC hardware platform and NIOSII software, can achieve the communication between board and PC, and control AES module.Firstly, the background of design, FPGA development process, development environment and tools are introduced.Then, the overall system design and implementation, including the AES algorithm realization, the configuration of the hardware system and software systems programming, are all explained. Finally, introduces the host machine design, system simulation and hardware debugging.更多还原