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基于RoF系统的低噪声放大器的设计

The Design of the Low-Noise Ampliifer for RoF System

【作者】 李伉

【导师】 游彬;

【作者基本信息】 杭州电子科技大学 , 电路与系统, 2012, 硕士

【摘要】 目前,各种无线通讯设备越来越多,应用也越来越广泛。Wi-Fi,RFID等技术的广泛应用对无线设备的要求越来越高。对于整个接收机来说,接受信号的灵敏度、辐射大小、接受信号的距离、噪声系数NF等指标都是需要设计者需要考虑的目标。在无线通讯系统中,处于接收机最前端的低噪声放大器是决定接收机噪声性能和灵敏度的关键部件。低噪声放大器位于接收机的最前端,它的性能直接影响到整个系统的好坏。就低噪声放大器电路设计而言,由于低噪声放大器一般与天线直接或天线后的滤波器相连,为了最大程度的信号传输,就需要放大器的输入端与它们很好的匹配。就低噪声放大器的制造工艺而言,CMOS工艺由于集成化的优势突出,有效的降低了成本。利用CMOS工艺制作性能优良的LNA已经成为研究重点。本文主要做了如下工作:首先,从MOSFET管的特性入手,分析了单管的电压电流特性,阐述了共源放大器、共栅放大器和源极跟随器的电路特性。然后叙述了基本的噪声原理,器件的噪声模型和MOSFET管的噪声分析方法。最后叙述了系统设计中对低噪声放大器的性能要求,分析了低噪声放大器的设计指标。其次,分析对比了近年来有关窄带低噪声放大器论文的各种设计结构,同时总结了近年来窄带低噪声放大器设计的优化方法。本文应用90nm IBM CMOS工艺,采用Cadence软件完成窄带低噪声放大器的设计,完成了电路图仿真、Corner分析、版图绘制、DRC、LVS以及后仿真,并提交流片。最后论文提出了一种新型电路结构。该电路结构可以通过调节控制电压,使电路在1.9GHz到2.4GHz频段内谐振在不同的频点,在每个频点处S11<-15dB,S22<-15dB,S21>15dB,NF<2dB,满足设计要求。再次,分析总结了宽带低噪声放大器不同的设计方法,并对各个方法的优缺点进行对比。文中应用90nm CMOS工艺,利用Cadence软件完成宽带低噪声放大器的设计,完成了电路图仿真、Corner分析、版图绘制、DRC、LVS以及后仿真,并提交流片。最后,本文提出了一种应用噪声抵消技术的新型电路结构。此电路在2GHz到4GHz的带宽范围内S11和S22均小于-10dB,NF<-2.4dB,S21>15dB,噪声系数和增益都有了提高。最后对芯片进行了PCB板内测试,分析了电路测试的结果,为以后电路设计提供了设计经验。

【Abstract】 Currently, there are a variety of wireless communications equipments, which have beenwidely used. Wireless devices must be improved because of the application of Wi-Fi, RFID andother technology. For the receiver, the most important parameters for the designer are the receivedsignal sensitivity, radiation, size, distance and noise figure (NF). In wireless communicationsystems, the low-noise amplifier,at the front of the receiver, is a key components that determinethe receiver noise figure.Low-noise amplifier is located in the front of the system. Its performance directly affects thequality of the entire system. Because the low noise amplifier is connected to the antenna, the inputand output of the LNA must be matched to 50Ohm for the maximum signal transmission. Atpresent, CMOS technology is conducive to integration and reduces the costs. The use of CMOStechnology has become the focus of the LNA. The main contributions of this paper are as follows:Firstly, we analyzed the characteristics of the MOSFET, and the relationship between thevoltage and current. The applications of the MOSFET have been shown includingcommon-source Amplifier, common-gate Amplifier and source Follower. On this basis, the noisemodel and MOSFET noise analysis have been shown. Then we explain the important role of theLNA in the system and the design parameters. The results are S11<-15dB, S22<-15dB, S21>15dB,NF<2dB.Secondly, the LNA in the recent paper in the IEEE have been analyzed in the paper. We findthe design ways of the LNA, and various design structures. The optimization method has beenshown in the paper. According to the design requirements, a narrow-band LNA has been designedin the paper by Cadence. We use 90nm IBM CMOS technology, and complete the circuitsimulation, corner analysis, DRC, LVS and post simulation. The results of the simulation are goodfor the design. A new low noise amplifier has been designed. The input and output impedancematching networks are achieved with extra variable capacitor controlled by the voltage. Thevariable capacitors used in the circuit design can make the LNA operate at some key frequencybands between 1.9GHz and 2.4GHz.Thirdly, the wide-band LNA in the recent paper has been analyzed. We comparative thedesign method of the LNA, and various design structures. The several different circuitarchitectures have been shown in the paper. According to the design requirements, a wide-bandLNA has been designed in the paper by Cadence. We use 90nm IBM CMOS technology, andcomplete the circuit simulation, corner analysis, DRC, LVS and post simulation. The results of the simulation are good for the design. We design a new circuit architecture that can improve theperformance of the noise and increase the gain of the circuit. This circuit has been verified bysimulation. The results are S11<-15dB, S22<-15dB, S21>15dB, NF<2dB, the gain and noisefigure are improved.Finally, the PCB of the IC has been tested. We analysis the results of the test circuit toimprove the experience of the circuit design.

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